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vhdl code for serial communication

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j hemangini

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vhdl code for siso

I got this serial in serial out vhdl code , but please tell me how it will work. Because i am not getting any response. Actually i want to communicate this board with hyperterminal and want to display on LCD, what i m writing on hyperterminal.
If someone has code for it then please post it.
Thank you.
 

kvingle

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vhdl code for serial in serial out shift register

where is the code....?
 

j hemangini

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siso vhdl

This is the code which i got on my mail id.

/////////////////////////////

library ieee;
use ieee.std_logic_1164.all;

entity SISO is
port (clk : in std_logic;
rst : in std_logic;
s_in : in std_logic;
s_out : out std_logic);
end SISO;

architecture s1 of SISO is
begin
process(clk,rst,sin)
begin
if(rst=\'0\') then
sout <= 1\'b0;
elsif(clk=\'1\' and clk\'event) then
sout <= sin;
end if;
end process;
end s1;
 

kvingle

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siso vhdl code

j hemangini said:
I got this serial in serial out vhdl code , but please tell me how it will work. Because i am not getting any response. Actually i want to communicate this board with hyperterminal and want to display on LCD, what i m writing on hyperterminal.
If someone has code for it then please post it.
Thank you.

the SISO code looks fine...(except the unwanted '\' syntaxes )

But to archieve the desired communication between board and hyperterminal you'll have to code a UART for serial communication and not a SISO.
 

j hemangini

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serial communication uart vhdl

I have used this code removing this unwanted syntex ' \' . Then tell me what i will get if i use this code? Because i am not getting or may be that i am not understanding any response. And if u can provide me code for my problem then please help me.
Thank you.
 

kvingle

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serial input controller vhdl

what do you mean by not getting any response
if you simulate this code then you will a get signal delayed by one clk. That is what a SISO hardware is supposed to do.

so s_out will be an delayed version of S_in.

what you need for serial communication is an UART. you can find code of UART at www.opencores.org .
 

j hemangini

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siso in vhdl

Ok , i try to find code on that web site. Thanks for the information.
 

j hemangini

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vhdl code for siso shift register

Hi kvingle,
I could not get any VHDL code for UART from the website WWW.OPENCORES.org.
I have also created my account on that website. Please tell me how can i find that code.
 

kvingle

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vhdl - output depending on clock pulse
 

j hemangini

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vhdl siso

Is this type of communication is possible in spartan-3a starter kit? I am not getting uart in this kit.
 

kvingle

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shift register serial out vhdl

yes. It is possible in kit the you are having...you should have RS-232 port (DB-9) connector already mounted on the PCB. refer to the documentation of your kit to know the RxD, Txd pin details..
 

sree205

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serial input in vhdl

Usually, SISO is supposed to take the serial input and send out the serial output. Depending on the delay that you need between ur input and output, the width of the register used will vary too.

For example, if u want to have a 8 clock pulse delay between ur input and output, use a 8-bit shift register,where input is fed into the LSB and output is taken out of the MSB or vice-versa
 

j hemangini

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vhdl code lcd serial

I got the vhdl code. That link was really very helpful for me. But now i m confused that what should be the pin outs for IntRx_N , IntTx_N ,Addr (1 to 0), DataIn(7 to 0) , DataOut (7 to 0) etc . Because i could not find pinouts for all these. I know only pinouts for RxD & TxD.
 

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