vhdl code for pulse generator

[kk_victory]

pulse generator vhdl

hi venkat
I have tried ur code but it is showing
so many errors. bcoz i m using xiink ISE 7.1
some functions are not supporting. I m giving
this how I implement in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity puls is
Port ( clk : in std_logic;
clk_div : out std_logic);
end puls;
architecture Behavioral of puls is
begin
process
begin
clk <= '1' ;
500000 ns ;
clk <= '0' ;
500000 ns ;
end process ;

end Behavioral;




Synthesis report

* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/rtl/puls.vhd" in Library work.
Entity <puls> compiled.
ERROR:HDLParsers:1402 - "C:/rtl/puls.vhd" Line 38. Object clk of mode IN can not be updated.
ERROR:HDLParsers:164 - "C:/rtl/puls.vhd" Line 39. parse error, unexpected INTEGER_LITERAL
ERROR:HDLParsers:1402 - "C:/rtl/puls.vhd" Line 40. Object clk of mode IN can not be updated.
ERROR:HDLParsers:164 - "C:/rtl/puls.vhd" Line 41. parse error, unexpected INTEGER_LITERAL
WARNING:HDLParsers:1406 - "C:/rtl/puls.vhd" Line 36. No sensitivity list and no wait in the process
-->

Total memory usage is 74824 kilobytes

Number of errors : 4 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

 

[ieropsaltic]

vhdl pulse generator

First, you can't assign a value to an input port. You can assign to output or inout ports.

To cause a delay, you can either use wait for 5000ns; inside a process but then you can't use a sensitivity list. or you can use ck<= '1' after 5000ns;

But be careful that delays are not synthesizable.

 

[FvM]

pulse generator vhdl code

But be careful that delays are not synthesizable.

Indeed. So why do you suggest it at all for a Xlinx ISE design?

Actually, a pulse generator implementation for a FPGA must use an external clock as time base. It would typically use a clock synchronous process and a delay counter or a state machine to achieve the intended timing. I'm pretty sure that Xilinx has some simple design examples of that kind.
.