vhdl code for pulse generation of pw=1ms

[kk_victory]

pulse generator in vhdl

Hi guys
I have implemented vhdl code for generating a pulse
of following specifications
PW= 1ms
i.e. 1ms=on & 1ms=off

Means it is 50% duty cycle.

entity pulse is
Port ( clk : in std_logic;
res : in std_logic;
clk_div : out std_logic);
end pulse;


architecture Behavioral of pulse is
signal count : integer;
signal temp : std_logic;

begin
process(clk,res)
begin
if res='1' then

temp <='0';
count <= 0;

elsif (clk'event and clk='1') then
if (count = 40000) then
temp <= not temp;
count <=0;
else
count <= count +1;

end if;
end if;
end process;
clk_div <= temp;

end Behavioral;

But Im not getting proper PW=1ms I m using 40 MHz Clock. I have simulated in Model sim
Plz Let me favour

 

[FvM]

verilog code for pulse generation

Please continue your previous thread. I think 40000-1 would be correct.