Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

vhdl code for left shifter with variable

Status
Not open for further replies.

rahulzambre

Newbie level 2
Joined
Nov 19, 2005
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
plz give me vhdl code for left shifter with variable as soon as possible. it's urgent
 

maksya

Full Member level 3
Joined
Jun 2, 2005
Messages
151
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,256
Code:
LIBRARY IEEE;
    USE IEEE.std_logic_1164.all;

ENTITY shift_reg IS
GENERIC(number_of_bits : integer;
       );
PORT(     reset : in std_logic;
     init_value : in std_logic_vector(number_of_bits-1 downto 0); -- outside of this block
            clk : in std_logic;
        data_in : in std_logic;
       data_out : out std_logic
    );
END shift_reg;

architecture behave of shift_reg is
begin

process(clk)
variable reg: std_logic_vector(number_of_bits-1 downto 0); 
variable i: integer;
begin
if reset = '1' then
   reg := init_value;
elsif rising_edge(clk) then
   for i in number_of_bits-1 downto 1 loop
      reg(i):=reg(i-1);
   end loop;
    
   reg(0):=data_in;
end if;

data_out <= reg(number_of_bits-1);
end process;

end behave;

it is possible that this code has some synthax mistakes. Sorry, but I have wrote it without having any tool.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top