vhdl code for Image processing

[electrotamil]

Hi every one:smile:
I'm trying to write a vhdl code for image processing application such as median filter in xilinx 10.1. i have converted my image into text file having array of hex codes using data converter and i read that file using read command. but i got a problem while writing the file. because i dono how to write result file in array format su ch as

25 FD F3 05 01 F9 FE 1E 24 EE
12 FA EF FC 12 23 FC 08 0F CC
EF F9 EE F7 1F 49 29 12 EA DC
F6 FC F9 07 04 0E 38 31 E0 0D
F8 FC F9 F0 C8 04 2D D9 E2 1D
EE 03 E6 C3 EA 15 0C CD FE 1A
DE 03 D2 D4 EB 17 FE DC 0C 39
DC FB D7 DB C5 0A EB DD 11 37
F4 EF C4 D7 C8 04 2A 02 14 07
FD ED BA C9 E6 0B 2A 20 FB E5

i used the following code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity image is
generic
(
WIDTH : integer := 256;
HEIGHT : integer := 256 -- IMAGE_MEMORY_SIZE
--ADDR_BUS_WIDTH : integer := 16
);

port(clk,en:in std_logic;
INPUT_FILENAME : string := "lena.txt"; -- Note: in Test Bench Waveform, file name is -9999, so must be modified
OUTPUT_FILENAME : string := "result.txt");
end image;

architecture Behavioral of image is
file ifile:text is in "C:\Users\tamil\Desktop\image\lena.txt";
file ofile:text is out "C:\Users\tamil\Desktop\image\result.txt";
begin

process(clk,en)
type tarray is array(0 to width*height-1)of bit;
variable myline:line;
variable i:tarray;
variable b:tarray;
begin
if clk'event and clk='1' then
if en ='1' then
while not endfile(ifile)loop
readline(ifile,myline);
for n in 0 to 255 loop
read(myline,i);
b:=i;
end loop;



for m in 0 to 255 loop
write(myline,b(m));
end loop;
writeline(ofile,myline);
end loop;
end if;
end if;
end process;
end Behavioral;



but it gives in single column answer only.
more over i want to know how to read n process array of datas such as shown above n print like same
also can u any one please suggest me the corresponding command or solution for this problem:wink:

 

[TrickyDicky]

This code is only suitable in simulation. It is not suitable for implementation on an FPGA.

 

[electrotamil]

then what to do sir ?
can u suggest me the file manipulating commands in vhdl to solve?
or what shoud i do next? please suggest me something......

 

[TrickyDicky]

No file manipulation is possible on FPGA. I suggest you go back to digital logic basic and learn how to implement a ROM.

 

[153rd]

A few days ago I had the exact same problem. I also used my code in a process:
txt_inprocess(CLK, write_en)

begin
if rising_edge(CLK) then
if write_en <= '1' then
while not((endfile(Datafile))) loop
Readline(Datafile, L);
Read(L, mem_data);
TXTRAM(i) <= mem_data;
i <= i +1;
end loop;
end if;
end if;
end process;

Where TXTram is of type RAMTYPE
type RAMTYPE is array(15 downto 0) of std_logic_vector(95 downto 0);

And datafile declaration:

File Datafile : text open read_mode is "GPUdata.txt";

 

[TrickyDicky]

This code is NOT suitable for implementation on an FPGA.

 

[153rd]

But it does work in a testbench, what happens if you try to implement this anyway?

 

[TrickyDicky]

You cannot do ANY file IO for synthesis (you can use it to initialise a ROM). Textio is mainly used for testbenches.
Look up the manufacturers code templates for RAMs and ROMs.

 

[praveenvanaparthy]

hi ,
Am also have same problem am trying to write code in verilog.

my code is compiled successfully and simulated also. but doesn't create output file
am trying to write the data in input file into output file. but its not created any output file.
i made some changes also using commands like:
$writememb(".txt", w);
$fopenw();

but its not works properly.


my code is here:
module txtrd(in1,out1,clk);
input [3:0] in1;
reg [3:0] in ;
output out1;
reg[3:0]out1;
input clk;
reg [3:0] temp [0:15];
integer i,file;

initial
begin
$readmemb("input1.txt",temp);
end

always @(posedge (clk))
begin
for (i=0;i<=15;i=i+1)
begin
in = temp;
out1=in;

end

file=$fopen("output1.txt", out1);
for (i=0;i<=15;i=i+1)
begin
$display(file,"%b", out1);
end
end
endmodule

any changes is need for this. please tell me.


and another doubt is is there any possibility to read image directly into verilog, and is it
synthesizable and is it possible to dump on fpga.

please tell me ..