vhdl code for dividing two number

[mina.nms]

hi
would you plz help me?
what is the problem with this vhdl code for dividing two numbers by state machine?
Thanks

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_STD.ALL;
 
 
entity divi is
    Port ( a,b : in  STD_LOGIC_VECTOR (15 downto 0);
           clk,e_in,res : in  STD_LOGIC;
           e_out : out  STD_LOGIC;
              div_out : out STD_LOGIC_VECTOR (15 downto 0);
            mod_out  : out STD_LOGIC_VECTOR (15 downto 0));
end divi;
 
architecture Behavioral of divi is
  type state is (init,divid);
  signal s_reg, s_next : state;
  signal div1,b1,dive : Unsigned (15 downto 0);
  signal mod1,mode: Unsigned (15 downto 0);
  
begin
  process (clk,res)
  
  begin
      if (res ='1') then
        s_reg <= init;
        elsif (clk'event and clk='1') then
        s_reg <= s_next;
      end if;
    end process;
    
  process (s_reg,div1)  
  
  begin
     
  case s_reg is
  
       when init =>  div1 <="0000000000000000";
                     b1 <= unsigned (b) ;
                      mod1 <= unsigned (a) ;
                            e_out<='0';
                       --if (e_in ='1') then
                       s_next <= divid;
                         -- end if;
                    
         when divid => if (mod1>=0)then
                       mod1<=mod1-b1;
                       div1<=div1+1;
                            else
                            mode<=mod1+b1;
                           dive<=div1-1;
                            
                            --div_out <= STD_LOGIC_VECTOR (dive);
                      --mod_out <= STD_LOGIC_VECTOR (mode);
                              
                            e_out <='1';
                       --s_next <= init;
                            end if;
                            
                       
    end case;
    
    end process;
   
                        
end Behavioral;

---

 

[DRO]

Hi,
First I think that you might have some latches from your combinatory process (the state machine).
They are some signals missing in the sensitivity list of your second process.
Second I don't really understand how you do the division. Do you got some kind of errors
or something?

 

[nick123]

Are You asking for Greatest Common Divisor Code??which is the largest positive integer that divides both numbers without remainder.

 

[ads-ee]

As DRO points out you have missing signals in your sensitivity list. You are missing signal assignment for all of the outputs in each branch of the FSM combinational process, that will produce latches as outputs not defined in a branch will need to hold their current state when the FSM takes that branch.

This is the reason why so many people use the single (clocked) process FSM style, it avoids these two process FSM style pitfalls.

Given the commenting out of the enable, I also suspect you were getting X's in your simulation so removed the enable to start the divide operation. The X out of the following code:

if (e_in ='1') then
  s_next <= divid;
end if;

was a result of not having an assignment for when e_in = '0' i.e.:

if (e_in = '1') then
  s_next <=divid;
else  -- specifies what to do when e_in = '0'
  s_next <= init;
end if;

As you didn't clarify exactly what was wrong, those are the first tier of problems in the code, that you need to correct.


Regards