VHDL code for decoder

[programmer36]

Need code to design 4 to 16 decoder using 3to8 decoder. Thanks.

 

[rajavel.rv]

u can use two 3:8 decoder; and using multiplexer option can chose the decoder;

3rd bit is help full for u for multiplexing;

1st 3:8 decoder: : 3rd bit is 0
0 000
0 001
--
--
0 111

2nd 3:8 decoder: : 3rd bit is 1
1 000
1 001
--
--
1 111

regards
rajavel.rv

 

[programmer36]

How to implement that in vhdl code? Since 2x 3to8 decoder have 6inputs while 4to16 decoder have 4inputs.
Thanks man.

 

[axcdd]

you can connect 2 bits to constant value

 

[rajavel.rv]

How to implement that in vhdl code? Since 2x 3to8 decoder have 6inputs while 4to16 decoder have 4inputs.
Thanks man.

Design a 3:8 decoder with selection signal; the input of (2 downto 0) (3 bit) u can connect easily now and rest of 3rd(4th bit) u can connect as a selection signal of both 3:8 decoder;

regards
rajavel.rv

 

[kaiserschmarren87]

You can implement in this way.

 

[std_match]

If the 3 to 8 decoders doesn't have an enable input, it gets more interesting.
I think I then need 5 of them to create a 4 to 16 decoder.

 

[rajavel.rv]

If the 3 to 8 decoders doesn't have an enable input, it gets more interesting.
I think I then need 5 of them to create a 4 to 16 decoder.

Nice, the designing of 3:8 decoder logic not required for the enable pin, but here the 4:16 decoder we need the enable pin for 3:8 decoder, its same like as a chip enable, device enable or block enable; this enable pin have only possible to used for tri-state logic of the 3:8 decoder, if its enable means its passing the output through the buffer, its not enable means the output have only high impedance state; as per design of kaiserschmarren87(previous post);

regards,
rajavel.rv

 

[FvM]

The exact logic function of the imagined 3-to-8 decoder hasn't been specified, but it would be rather unusual that the enable input is related to a tristate function. Review 74138 IC as an example of expectable decoder operation.