VHDL CODE Finding Max/Min of a sampled signal

[tigag]

Hi
Please,I need some help.
I need a VHDL program to find the maximum and minimum of a sampled signal during a certain time period(like 2 seconds). The sample frequency is 1 MHz.
Thanks

 

[shaiko]

1. Write a process that times your sampling window (2 seconds as you said) and raises a single clock flag at the end of each window.
2. Define 2 signals: "maximum" / "minimum". Make the default value of "maximum" (others => '0' ) and the default value of "minimum" (others => '1' ).
3. With each new clock compare the incoming value to the signals in step 2. If the incoming value is lower then "minimum" replace the current value of "minimum" with it. If the incoming value is higher then "maximum" replace the current value of "maximum" with it.
4. When the flag from step 1 comes, assert signals "minimum" and "maximum" to the outputs and reset them again to their default values.

 

[TrickyDicky]

Here try this code. It does exactly what you asked for:

---

Code VHDL - [expand]
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process
  variable max : integer := integer'low;
  variable min : integer := integer'high;
begin
 
  if NOW < 2 s then
    if input > max then max := input; end if;
    if input < min then min := input; end if;
  else 
    wait;
  end if;
 
  wait for 1 ms;
end process;

---

 

[FvM]

Here try this code. It does exactly what you asked for

I have difficulties to relate the sample frequency of 1 MHz to your suggestion. But I agree that the OP should tell more clearly if he wants to write synthesizable VHDL for FPGAs.

 

[shaiko]

TrickyDicky,

I assume the request was for a synthesizable code.
Also, your simulation code will search for min, max only within the first 2 seconds...
IMO, the OP's intention was to continue sampling indefinitely and assert the result EVERY 2 seconds.

 

[TrickyDicky]

TrickyDicky,

I assume the request was for a synthesizable code.
Also, your simulation code will search for min, max only within the first 2 seconds...
IMO, the OP's intention was to continue sampling indefinitely and assert the result EVERY 2 seconds.

I stuck the letter of his request.