libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;entity counter isport(x :instd_logic_vector(3downto0);
clk :instd_ulogic;
y :outstd_logic_vector(3downto0));endentity counter;architecture code_behavior of counter issignal a:std_logic_vector(3downto0);beginprocess(clk)beginif rising_edge (clk)then a<= x;endif;endprocess;process(x)beginif rising_edge (clk)thenif x <"1001"then y<=(a+"0001");
a<= a +"0001";elsif x >"1001"then y<=(a-"0001");
a <= a -"0001";else y<="1001";endif;endif;endprocess;endarchitecture;
It's also wrong to use x in the sensitivity list of a clocked process. It has no effect in hardware synthesis but causes simulation mismatch. What's your intention?