aahmadd
Newbie level 1
Hi,
I'm trying to write a code in VHDL that accepts 1 input ,other that the (clk and rst), and gives 2 different outputs.
e.g.
input is 11
outputs
a/ 0110
b/ 0011
in order. So if the first output was 0110 then second output will be 0011 and keeps going like that, never 2 same successive outputs, as long as the circuit is running.
Please help me.
Thanks in advance.
I'm trying to write a code in VHDL that accepts 1 input ,other that the (clk and rst), and gives 2 different outputs.
e.g.
input is 11
outputs
a/ 0110
b/ 0011
in order. So if the first output was 0110 then second output will be 0011 and keeps going like that, never 2 same successive outputs, as long as the circuit is running.
Please help me.
Thanks in advance.