vhdl both edge
It merely depends upon the Synthesis tool but I prefer if you do a clk and a not clk signal "this signal dissolves if the FPGa FF architecture support inverted clk input", in Xilinx coolrunner II CPLd you can use a rising_edge elsif falling_edge , you can even use .
-- Coolrunner II
if clk'event then
a <= b;
end if;
-- Works with XST
the code above will do a coolrunner II Macro if you used XST, this code will update 'a' each rising and falling edge 'true double data rate'.
This can not be implemented easy on the FPGA, i.e. you may use the MUX that Vomit informed you about. but your delay charactersitic will be very bad also if you did this you can not trust the timing analysis results, the main reason here is because you used a clock to do a MUX "note clock is linked to low-skew routes and you will have to spin it off to the CLB", however this is not the only way, you can improve that with some other techniques.
If you have separate signals "one rising_edge updated while the other falling_edge updated" try to declare a clkb signal that is 'not clk' i.e.
clkb <= not clk;
in your architecture "combinational part" and then you can declare clkb in the senstivity list and do whatever you want if your target is an FPGA " note DON'T TRY if rising_edge(clk) followed by elsif(risng_edge(clkb) this is trouble".
writing the code this way will save you the trouble of switching between "rising_edge and falling_edge" which leads to a better coding technique and you can trace your code much easier this way "it is always your choice".
I have tried this technique in LS and synplfy and it worked "i.e the inverter dissolved to a negative edge rising FF"
You can try the DLL/DCM CLK180 to replace a not clk but believe me you may get better result if you used the falling edge FF "routing delays even with global buffers but not always".
The only true double data rate FF in Xilinx FPGA are the FDDRSE in Virtex-II "and higher" an it doesn't exist in the CLBs it exists only on the IOB and this ofcourse limits its use also it can not be infered, so it must be instantiated. I believe it was developed to simplify the DDR RAM interface and to meet timing requirements for 400 Mb/s controller at 200 MHz clock "or so I used it for", I believe altra has some equivelant FFs but I didn't use that.
Thats all folks