[vhdl] both rising_edge(c) & falling_edge(c) in one proc

[vvsvv]

rising_edge vhdl

may I use both rising_edge(clk) and falling_edge(clk) in just one process?
or in one architecture? :wink: thx;

source code may just like this:

use ieee.std_logic_1164.all;
......
clk: std_logic;
......
if rising_edge(clk) then
out_a<='1';
elsif falling_edge(clk) then
out_b<='1' ;
end if;
.......
May I do so?
If I may , can these codes be synthesis?
thanks again! :roll:

 

[lucbra]

vhdl rising_edge

You can do, but synthesis will depend on your architecture. If your PLD architecture doesn't support clocking at both edges, you will find a different implementation (with probably not the desired outcome)

chears

 

[vomit]

rising_edge

Some synthesis tools can deal with

process(Clk)
begin
  if rising_edge(Clk) then
    signal1<=...
  end if;

  if falling_edge(Clk) then
    signal2<=...
  end if;
end process;

but doing what you're doing (elsif) is asking for trouble. Synthesis tools are not intelligent beings that know what you mean, they just match code to their conceptions of "clocked process". So it would be best to use the style above, or to be sure, to write two processes.

If you want to have a dual-edge-clocked flipflop (one single signal changed on both edges of the clock) - forget it, there is no such thing in any major FPGA technology.

If you want to have a similar effect, use the code above and add a multiplexer on the clock:

sig <= signal1 when Clk='1' else signal2;

 

[omara007]

vhdl falling_edge

If you want to have a similar effect, use the code above and add a multiplexer on the clock:

sig <= signal1 when Clk='1' else signal2;

I guess this line of code would result in a latch rather than a FF .. won't it ? .. in this case the latch can said to be another design prohibted thing in most cases ..

A question deserves to be mentioned .. what if the falling/elseif/rising code was intended to ASIC ?

 

[tlp71@hotmail.com]

vhdl rising_edge falling_edge

XILINX say that you FF of Virtex devices are Double Rate, this probably means that they can be used on both edge.
I can't understand how the mux work respect edge.
G.

 

[mc&amp;fpga]

2 rising_edge in one process

if you want to use it in one process it has problem & you lose one cycle
so its better to use them in two sepeared process.

 

[Black Jack]

vhdl rising_edge()

XILINX say that you FF of Virtex devices are Double Rate, this probably means that they can be used on both edge.
I can't understand how the mux work respect edge.
G.

I don`t know about Virtex, but CoolRunner II
have features - Dual Edge Flip-flop

And such processes are synthesizable (e.g. with $ynpIiFy)

 

[Husoo]

rising_edge falling_edge

sorry, but y do u need to do so? u drive 2 different signals... u can put them into seperate processes as usual. Omitting the reset:

process1(Clk)
begin
if rising_edge(Clk) then
signal1<=...
end if;
end process;

process2(Clk)
begin
if falling_edge(Clk) then
signal2<=...
end if;
end process;

No problem with synthesis.

 

[delay]

xilinx rising_edge

As a general rule, stick with SINGLE clock edge in entire design. This will make yor life helluva easy.

Delay (delayed by technology)

 

[bibo1978]

vhdl both edge

It merely depends upon the Synthesis tool but I prefer if you do a clk and a not clk signal "this signal dissolves if the FPGa FF architecture support inverted clk input", in Xilinx coolrunner II CPLd you can use a rising_edge elsif falling_edge , you can even use .
-- Coolrunner II
if clk'event then
a <= b;
end if;
-- Works with XST
the code above will do a coolrunner II Macro if you used XST, this code will update 'a' each rising and falling edge 'true double data rate'.
This can not be implemented easy on the FPGA, i.e. you may use the MUX that Vomit informed you about. but your delay charactersitic will be very bad also if you did this you can not trust the timing analysis results, the main reason here is because you used a clock to do a MUX "note clock is linked to low-skew routes and you will have to spin it off to the CLB", however this is not the only way, you can improve that with some other techniques.

If you have separate signals "one rising_edge updated while the other falling_edge updated" try to declare a clkb signal that is 'not clk' i.e.
clkb <= not clk;
in your architecture "combinational part" and then you can declare clkb in the senstivity list and do whatever you want if your target is an FPGA " note DON'T TRY if rising_edge(clk) followed by elsif(risng_edge(clkb) this is trouble".

writing the code this way will save you the trouble of switching between "rising_edge and falling_edge" which leads to a better coding technique and you can trace your code much easier this way "it is always your choice".
I have tried this technique in LS and synplfy and it worked "i.e the inverter dissolved to a negative edge rising FF"
You can try the DLL/DCM CLK180 to replace a not clk but believe me you may get better result if you used the falling edge FF "routing delays even with global buffers but not always".

The only true double data rate FF in Xilinx FPGA are the FDDRSE in Virtex-II "and higher" an it doesn't exist in the CLBs it exists only on the IOB and this ofcourse limits its use also it can not be infered, so it must be instantiated. I believe it was developed to simplify the DDR RAM interface and to meet timing requirements for 400 Mb/s controller at 200 MHz clock "or so I used it for", I believe altra has some equivelant FFs but I didn't use that.

Thats all folks

 

[jay_ec_engg]

falling_edge

Hi u can use two edge sensitive statements in a single proces theoratically... but as far as i know its not synthesizabkle at all...
Even if u will use two processes for two edge sensitive statements.. then try to wtrite the full code in each statement... use surecore... otherwise even after compiling and synthesiz.. ur program wont work properly in realtime....

jay