sumgupta89
Newbie level 4
hi frnds ..cn ne1 tell me how this logic iks working?
its basicaly a asynchronous fifo design in VHDL. here pnextwordtowrite and pnextwsordtoread are basially two 4 bit address strings and set_status bit is 1 bit(std_logic).The aim is to compare between their address values.but i am getting confused with the xor between addr_width-1 and addr_width-2. how this works???? and which bit they are basically comparing?????
CODE :
process (pNextWordToWrite, pNextWordToRead)
variable set_status_bit0 :std_logic;
variable set_status_bit1 :std_logic;
variable rst_status_bit0 :std_logic;
variable rst_status_bit1 :std_logic;
begin
set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor
pNextWordToRead(ADDR_WIDTH-1);
set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor
pNextWordToRead(ADDR_WIDTH-2);
Set_Status <= set_status_bit0 and set_status_bit1;
rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor
pNextWordToRead(ADDR_WIDTH-1);
rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor
pNextWordToRead(ADDR_WIDTH-2);
Rst_Status <= rst_status_bit0 and rst_status_bit1;
end process;
process (Set_Status, Rst_Status, Clear_in)
begin
if (Rst_Status = '1' or Clear_in = '1') then
Status <= '0'; --Going 'Empty'.
elsif (Set_Status = '1') then
Status <= '1'; --Going 'Full'.
end if;
end process;
its basicaly a asynchronous fifo design in VHDL. here pnextwordtowrite and pnextwsordtoread are basially two 4 bit address strings and set_status bit is 1 bit(std_logic).The aim is to compare between their address values.but i am getting confused with the xor between addr_width-1 and addr_width-2. how this works???? and which bit they are basically comparing?????
CODE :
process (pNextWordToWrite, pNextWordToRead)
variable set_status_bit0 :std_logic;
variable set_status_bit1 :std_logic;
variable rst_status_bit0 :std_logic;
variable rst_status_bit1 :std_logic;
begin
set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor
pNextWordToRead(ADDR_WIDTH-1);
set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor
pNextWordToRead(ADDR_WIDTH-2);
Set_Status <= set_status_bit0 and set_status_bit1;
rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor
pNextWordToRead(ADDR_WIDTH-1);
rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor
pNextWordToRead(ADDR_WIDTH-2);
Rst_Status <= rst_status_bit0 and rst_status_bit1;
end process;
process (Set_Status, Rst_Status, Clear_in)
begin
if (Rst_Status = '1' or Clear_in = '1') then
Status <= '0'; --Going 'Empty'.
elsif (Set_Status = '1') then
Status <= '1'; --Going 'Full'.
end if;
end process;