VHDL : asynchronous fifo design troubleshoots

[sumgupta89]

hi frnds ..cn ne1 tell me how this logic iks working?
its basicaly a asynchronous fifo design in VHDL. here pnextwordtowrite and pnextwsordtoread are basially two 4 bit address strings and set_status bit is 1 bit(std_logic).The aim is to compare between their address values.but i am getting confused with the xor between addr_width-1 and addr_width-2. how this works???? and which bit they are basically comparing?????

CODE :
process (pNextWordToWrite, pNextWordToRead)
variable set_status_bit0 :std_logic;
variable set_status_bit1 :std_logic;
variable rst_status_bit0 :std_logic;
variable rst_status_bit1 :std_logic;
begin
set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor
pNextWordToRead(ADDR_WIDTH-1);
set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor
pNextWordToRead(ADDR_WIDTH-2);
Set_Status <= set_status_bit0 and set_status_bit1;

rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor
pNextWordToRead(ADDR_WIDTH-1);
rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor
pNextWordToRead(ADDR_WIDTH-2);
Rst_Status <= rst_status_bit0 and rst_status_bit1;
end process;


process (Set_Status, Rst_Status, Clear_in)
begin
if (Rst_Status = '1' or Clear_in = '1') then
Status <= '0'; --Going 'Empty'.
elsif (Set_Status = '1') then
Status <= '1'; --Going 'Full'.
end if;
end process;

 

[TrickyDicky]

Why dont you simulate it in your favourite simulator?

 

[sumgupta89]

i am using xilinx ise 10.1..bt favourite simulator !!!!!!!! wt does dt mean???????

 

[TrickyDicky]

Modelsim? ActiveHDL? GHDL?

You can simulate the code without synthesising it.

 

[supercat]

Work out the counting sequence for graycode counters for your stuff/fetch counters and you will observe that when the counter is exactly 1/4 full, the two two bits of the two counters will have one relationship, and when it's 3/4 full they'll have another. The 1/4-full signal will also be active at some other times when the queue isn't exactly 1/4 full but holds between 1 item and N/2-1, and may output some runt pulses, but it is guaranteed to be solidly high sometime during the interval when the number of items goes from N/4-1 to N/4+1, and never be high when the number of items is N/2 or greater. The 3/4-full signal behaves similarly. The status latch may sometimes go metastable, but will never be metastable any time its condition matters.

On the other hand, there is a 'gotcha' with a fully-async queue: the full/empty outputs must be externally synchronized in the time domains of the stuffer/fetcher. This will limit the maximum data throughput that can be achieved, since the stuffer must wait a synchronization delay after each put to see if there's room for more, and likewise with the fetcher. Having the stuffer keep a synchronized copy of the fetcher's pointer and vice versa, and having them do their comparisons based on those, would avoid that limitation.