VHDL-AMS Sigma Delta Modulator

[gsuarez]

Hi,

I'm currently working on a 2nd Order Sigma Delta Modulator (SDM) in VHDL-AMS. I'm using hAMSter and Simplorer as simulators. I was able to simulate correctly a 1st Order SDM but when I try the Second Order Model the system becomes unstable. The model is nonideal, the integrators are implemented using a unit transient equations dependent on the OTA parameters. I'm using a coherent input signal of -3dB 30.1kHz and oversampling ratio of 48 for a maximum input frequency of 200KHz (sampling frequency of ~19.2MHz). I have the same system in simulink and works fine. If someone can help me please let me know.

George

 

[feel_on_on]

are u coding a Delta-Sigma modulator with VHDL-A/?

 

[gsuarez]

Actually, I coded the model in Verilog-A and VHDL-AMS. Never tried VHDL-A. I got it working for both, (Verilog-A in Cadence Spectre and VHDL-AMS in Ansoft Simplorer v6&v7). If you want more details let me know. Thanks for the post and sorry for the huge delay in replying.

George