[SOLVED] VHDL alias on 2D arrays

[dpaul]

I have not referred to the LRM, but it looks like 2D arrays (type can be any) cannot be referenced via alias.

Or is my understanding incorrect?

 

[TrickyDicky]

Anything can be aliased in VHDL.
Do you have an example thats not working?

 

[dpaul]

I will get back to you tomorrow. A colleague of mine complained about this.
I am modifying my TB to access a 2D array of type std_logic_vector located somewhere deep in my design, to see what the compiler has to say.
My colleague uses Xilinx xsim, I use Modelsim. Can that create a difference?

 

[TrickyDicky]

So this is a question also about external names, not necessarily aliases.

--- Updated Oct 19, 2021 ---

I would suggest anything that involves Xilinx tools creates a difference.

 

[dpaul]

@TrickyDicky,
Yes it was to ally the external name with an alias statement (I was not strict with the thread name).

My colleague had declared the alias as a global signal and the compiler complained about it.

 ** Error (suppressible): C:/work/../../../*_tb.vhd(201): (vcom-1309) Target of the external name must be elaborated before the external name is evaluated.

I used the following way:

.
.
type arr_64b_17d is array (16 downto 0) of std_logic_vector(63 downto 0);
signal axi_rd_arr_tb : arr_64b_17d;

begin

  proc1: process(...)
    begin
    .
    .
    end process proc1;
  .
  .
  .
    alias_test_p: process(clk)
        alias axi_rd_arr is <<signal top_inst.submod1.submod2.rd_data_arr : arr_64b_17d>>;
    begin
        if rising_edge(clk) then
            axi_rd_arr_tb <= axi_rd_arr;
        end if;
    end process alias_test_p;
  .
  .

 

[TrickyDicky]

The error is correct - external names need to have knowledge of the hierarchy, hence you cannot use an external name into an entity that hasnt been instantiated yet. So using it as a global signal inside a package is not going to work.