VHDL 360, Create Your First Model for a Simple Logic Circuit

[amraldo]

We published the 2nd tutorial of our free VHDL course for newbies @ Embedded Tips from Amr Ali: VHDL 360, Create Your First Model for a Simple Logic Circuit
--
Amr Ali

 

[TrickyDicky]

The use of std_logic_arith/std_logic_signed/unsigned immediatly puts me off.

When will be people realise these package went obsolete 15 years ago?

Plus you're missing std_logic_1164 on page 17

 

[shmoib]

I don't think std_logic type packages has vanished or will vanish in the near future, I still see different designs that uses these packages.
As for slide 17, the std_logic_unsigned type -which is used in the example there- already includes the std_logic_1164 thus no need to include it again.

I hope things are clear now.

Regards,
Mohamed Samy

The use of std_logic_arith/std_logic_signed/unsigned immediatly puts me off.

When will be people realise these package went obsolete 15 years ago?

Plus you're missing std_logic_1164 on page 17

 

[TrickyDicky]

The only reason designs exist with std_logic_arith/unsigned/signed exist is because tutorials like this show people how to use it. Then people never change their habits.

Also, just becaise std_logic_unsigned uses the 1164 package, does not mean the design file includes it as well.

 

[permute]

Well, that and because of things like simplified addition/subtraction and indexing. numeric_std doesn't allow std_logic_vector + std_logic_vector, or std_logic_vector + integer. numeric_std also doesn't have conv_integer. These are the other reasons std_logic_unsigned still exists.

 

[FvM]

Well, that and because of things like simplified addition/subtraction and indexing. numeric_std doesn't allow std_logic_vector + std_logic_vector, or std_logic_vector + integer.

The "simplified arithmetic" encourages using a wrong type where a correct type could be used without much effort but bringing more clarity.

numeric_std also doesn't have conv_integer

Well, it has to_integer().

 

[permute]

And that's my point -- the numeric_std puts more emphasis on being academically correct. If you try to force someone into writing code in a specific way, don't be surprised when they look for an easier way. For SLU, it also makes coding more similar to Verilog. I don't use SLU, but I certainly see the appeal every time I see a "to_integer(unsigned(select))" or "std_logic_vector(unsigned(x)+1)". The latter is usually because the signal is used in 10+ places as a std_logic_vector, and in 1 place as an unsigned.

 

[TrickyDicky]

Ok

Tell me how I can do signed and unsigned maths on the same std_logic_vector in the same file?
And isnt being academically correct the whole point?

If you're seeing to_integer(unsigned(slv)) then someone really doesnt understand typing.

With correct typing of ports, there is no need for all of the type conversions.

TYPING IS VHDL's STRENGTH!

 

[vipinlal]

I think you cannot avoid the synopsis libraries fully from all your future designs. I agree that std_logic_arith/unsigned are not IEEE standardized libraries but they are useful in some designs. For example if I am instantiating a memory and the memory is supposed to posses generic values then it is suitable to use SLV. But if I am designing a math processor and need to do lot of calculation on -ve numbers then I can stick to numeric_std.
And beginners obviously use arith/unsigned libraries because most of the examples in net are based on them.Even university tutorial websites dont use numeric_std most of the times.So if you want to at least, slightly change the situation then you should start writing some good tutorial for the beginners.Complaining here wont solve anything.

 

[amraldo]

Guys,
First of all, thanks a million for the rich discussion and the variety of opinions.
Please, I feel there is some tense in here. The idea of the whole post is to share knowledge. We made VHDL 360 as a way to help newbies.
Again, I apologize if my post made any tense.
--
Amr

 

[FvM]

Even university tutorial websites dont use numeric_std most of the times.So if you want to at least, slightly change the situation then you should start writing some good tutorial for the beginners.Complaining here wont solve anything.

My point is, that the Synopsys legacy std_logic_arith etc. libraries can be completely avoided, if you want to. If you don't like to type to_integer(unsigned(slv)) frequently, you can write your own shortcut for it. The long winded expression has the advantage of clearing all doubts about the nature of involved signals, however. The interesting question is, why a slv has been used for a signal that's apparently an unsigned quantity in this place? Either because the author used lazy typing (can be corrected easily), or (more likely) because he needed to interface 3rd party IP, that uses slv as universal interface type. Unfortunately, most vendor IP does it in all places, not only where it obviously applies.

I don't see a need to complain each time, the sticky libraries are used. But I'm not engaged in HDL programming education.

Personally, I'm using std_logic_xxx in most old projects. Unfortunately, new projects are often inherited from those, so they continue the bad habbit. Even more unfortunately, I make new guys, who have to maintain these projects, adapting the bad practice. It's time to break the chain.

 

[permute]

TD -- addition/subtraction for both unsigned and signed are done using the same hardware.

The issue is that std_logic_vector (instead of either signed or unsigned) is the de-facto standard. As soon as you have to deal with anyone else's code, you run into issues with trying to get creative with ports.

the to_integer comes about when you have select lines and want to do something like x(select). This fails because the index must be an integer. thus x(to_integer(select)) seems logical, but fails. select might be signed or unsigned. the result is x(to_integer(unsigned(select))).

As for academically correct -- many other languages (both HDL and programming) have some convience features. VHDL goes out of its way to remove these.


I personally use numeric_std. But for the above reasons, I can see the appeal std_logic_unsigned would have for some users.

amraldo -- I don't think there's any real tension.

 

[amraldo]

A storm in a cup

 

[TrickyDicky]

I think you cannot avoid the synopsis libraries fully from all your future designs. I agree that std_logic_arith/unsigned are not IEEE standardized libraries but they are useful in some designs. For example if I am instantiating a memory and the memory is supposed to posses generic values then it is suitable to use SLV. But if I am designing a math processor and need to do lot of calculation on -ve numbers then I can stick to numeric_std.
And beginners obviously use arith/unsigned libraries because most of the examples in net are based on them.Even university tutorial websites dont use numeric_std most of the times.So if you want to at least, slightly change the situation then you should start writing some good tutorial for the beginners.Complaining here wont solve anything.

In quartus at least, you can instantiate RAMs from any bit type. I have created rams from integers, unsigned, signed, sfixed and ufixed before without any problems. I have a large design that takes up 75% of an Arria 2 GX 125 without a single use of a synopsys library.

@permute: the convenience features are there - you just have to create them youself. Just in this case synopsys created some packages that went against the spirit of the whole language. Now courses like this teach the use of synopsis and most of them will never learn any different, and we have the vicous circle. VHDL is meant to be typed - it is clearer and alot more functional.
Just create a library with a function to_int that hides the long winded conversion and you're away. Even better, dont use std_logic_vectors when you dont need to (like in/outs from an entity).

 

[permute]

I'm not sure how much better it is to re-define the language for your own use. Its obvious what std_logic_unsigned does because its a popular package. "vhdl_fixes_pkg.vhd" might not really say anything about what the user "fixed" about vhdl. Though I do like the idea of a "to_idx" function mapping slv to positive.

In Xilinx, you can also use any type. I've even made a RAM from an array of records. That prevents the need to write multiple RAMs, making it easier to update the read/write logic.