VHDL 16x4 Mux? Whats the code for it?

[imconfused]

How do you code a 16x4 MUX? I have to code a compressor, I know how to code the smaller mux such s 4x1 but I have no clue how to code this. Help please?

 

[TrickyDicky]

do you mean 16 inputs and 4 outputs? or 16 inputs and 1x4bit output?

For the first case, that would just be 4x 16x1 muxes.

 

[imconfused]

thanks!

I used 4 16x1 muxes and it seems to be working.

 

[kannansanjeev]

-- 16*1 MUX using 4 4*1 MUX
library ieee;
use ieee.std_logic_1164.all;
entity mux16 is
port(a:in std_logic_vector(0 to 15);sel:in std_logic_vector(0 to 3);
yut std_logic);
end mux16;
architecture mux16arc of mux16 is
component mux4 is
port(sel:in std_logic_vector(0 to 1);a:in std_logic_vector(0 to 3);
yut std_logic);
end component;
signal t:std_logic_vector(0 to 3);
begin
x1:mux4 port map(sel(0 to 1),a(0 to 3),t(0));
x2:mux4 port map(sel(0 to 1),a(4 to 7),t(1));
x3:mux4 port map(sel(0 to 1),a(8 to 11),t(2));
x4:mux4 port map(sel(0 to 1),a(12 to 15),t(3));
x5:mux4 port map(sel(2 to 3),t,y);
end mux16arc;