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| module vga_sync(pixel_x,pixel_y,hsync,vsync,video_on,clk,rst);
output [9:0]pixel_x,pixel_y;//total pixels
output video_on,hsync,vsync;
input clk,rst;
localparam HP=640;
localparam VP=480;
localparam VR=2;
localparam HR=96;
localparam HFP=48;
localparam VTP=33;
localparam HBP=16;
localparam VBP=10;
reg [9:0]hcount_reg,vcount_reg,hcount_temp,vcount_temp;
wire hsync_temp,vsync_temp;
reg hsync_reg,vsync_reg;
wire hend,vend,pixel_tick;
always@(posedge clk)
begin
if(rst)
begin
hcount_reg<=0;
vcount_reg<=0;
hsync_reg<=1'b0;
vsync_reg<=1'b0;
end
else
begin
hcount_reg<=hcount_temp;
vcount_reg<=vcount_temp;
hsync_reg<=hsync_temp;
vsync_reg<=vsync_temp;
end
end
assign hend=(hcount_reg==(HP+HFP+HBP+HR-1));
assign vend=(vcount_reg==(VP+VTP+VBP+VR-1));
always@(posedge clk)
begin
if(hend)
hcount_temp=0;
else
hcount_temp=hcount_reg+1'b1;
end
/*always@*
begin
if(posedge clk)
if(hend)hcount_temp=0;else hcount_temp=hcount_reg+1;
else
hcount_temp=hcount_reg;
end
*/
always@(posedge clk)
begin
if(hend)
if(vend)
vcount_temp=0;
else
vcount_temp=vcount_reg+1'b1;
else
vcount_temp=vcount_reg;
end
assign hsync_temp=(hcount_reg>=(HP+HBP)&& hcount_reg<=(HP+HBP+HR-1));
assign vsync_temp=(vcount_reg>=(VP+VBP)&& hcount_reg<=(VP+VBP+VR-1));
assign video_on=(hcount_reg<HP)&&(vcount_reg<VP);
//output
assign hsync=hsync_reg;
assign vsync=vsync_reg;
assign pixel_x=hcount_reg;
assign pixel_y=vcount_reg;
endmodule |