Make sure that you clear the D1, D2, D3, D9 violations to ensure that all flops are converted to scan flops. Modulewise, you need to write out the ND(undetectable faults) as well as the AU (ATPG untestable). If AU faults are more, then you need increase the abort limit.
If latches in the module are not transparent, then they must be made transparent. For this, you must OR the latch-enable signal from logic with the dft test_enable signal.
report the non-scannable flops for the module based on the clock domain. If the non-scannable flops are more, then we can increase the capture cycles, so that these elements can also be loaded.