Aug 11, 2007 #1 M mohdfayez Junior Member level 2 Joined Jun 29, 2007 Messages 22 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,417 Hi guyz, I have some very good material on STA, hope u find it useful
Aug 12, 2007 #2 H hoalu Newbie level 4 Joined Nov 7, 2004 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Vietnam Activity points 41 Thanks, it's easy to understand.
Aug 12, 2007 #3 L lvxinhaozi Newbie level 3 Joined Jul 18, 2007 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,292 Thank you very much.
Aug 12, 2007 #4 V vlsichipdesigner Full Member level 2 Joined May 9, 2007 Messages 134 Helped 17 Reputation 34 Reaction score 9 Trophy points 1,298 Location India Activity points 2,367 Dear Designers, my 2 cents... You will find a very good article regarding Static Timing analysis in the below mentioned link. In this you find good articles about falsepath, multicycle path and source synchronous paths explanations and scenarios. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/statictiminganalysis.html This article will discuss about the ways to solve setup and hold violations. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/solvesetupholdviolation.html The below mentioned article will discuss about the ways to model the onchip variation in Static timing analysis and qualify the design for robustness. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/ocv.html best regards, vlsichipdesigner https://www.vlsichipdesign.com [ASIC chip design School for Free access]
Dear Designers, my 2 cents... You will find a very good article regarding Static Timing analysis in the below mentioned link. In this you find good articles about falsepath, multicycle path and source synchronous paths explanations and scenarios. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/statictiminganalysis.html This article will discuss about the ways to solve setup and hold violations. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/solvesetupholdviolation.html The below mentioned article will discuss about the ways to model the onchip variation in Static timing analysis and qualify the design for robustness. https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/ocv.html best regards, vlsichipdesigner https://www.vlsichipdesign.com [ASIC chip design School for Free access]
Feb 5, 2009 #5 A armmips Member level 1 Joined Jan 25, 2009 Messages 38 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,406 It is very helpful. Thanks for sharing.