verolog netlist to rtl converter

[ram]

verilog netlist rtl

I am looking for a free netlist to rtl converter. What are the ways of doing this?. What tools support this what r the commands?

 

[pandora]

netlist to rtl

I think that simulator support netlist can do it
eg . Cadence Verilog-XL

 

[mvvijay78]

rtl converter

Hi Pandora,
Have u really worked on verilog XL.If u claim that the tool can do the netlist to RTL conversion can u explain how exactly it does that.I am not sure that the tool u have mentioned has the abitlity to do that.
Vicky

 

[z81203]

verilog to rtl converter

I don't understand the exactly meaning of 'netlist to rtl', I think it means 'schematic to netlist(rtl)'.
If I'm right, Cadence can do it in 2 way with IC & LDV.
1st use CSI, which meaning Cadence-Synopsys-Interface, in 'icds'.
2nd invoke XL in schematic of 'icds', you can find netlist file in ***.run1/ directory after compile it.

 

[rakko]

verolog

it is not possible to revert a netlist back to verilog. At least as of today no one has figured out how to do this. if you figure this out you probebly be the next billioner. Think about the problem or better yet compile a simple always block to netlist and then try to write a program to reverse it back to rtl to get an idea of what you are suggesting here. Actually, ASIC companies are so certain you can not do it that they give their netlist to their customers unprotected. They are sure they won't be able to make heads from tails even if they attempt to understand it.

 

[mvvijay78]

spice netlist using perlscript

Hi,
That's the point i wanted to bring out because when we do synthesis of a RTL based on the applied constarints the tool would have comeup with some topology by selecting from n numer of topologies for the same implementaton.So how can the RTL worked back.
Regards
Vicky

 

[z81203]

how to convert netlist to rtl

Never heard anyone can do from gate to rtl.

 

[pandora]

rtl code to netlist converter

hi mvvijay78
I have the same meaning with z81203
there may be functional every module in the netlist

 

[ram]

netlist to rtl conversion

I have achived this thing. What i did is i had written a perl script. The script will take verilog netlist as input. & will give RTL equivalent of that. How evevr the script is technology library specific.

 

[tony_taoyh]

cadence composer rtl

I have one simple question for it...

Any usage for the generated RTL codes?????

 

[funzero]

verilog-xl unprotected

there is noway from netlist to RTl.
lib info , timing info needed to convert.

 

[rakko]

Ram could you share your perl script with the rest of us here. i'm really interested in seeing how sophisticated your scripts is.

 

[andy2000a]

novas debussy , and Cadence composer can reading verilog netlist
convert to schematic ..

Added after 1 minutes:

by the way ,
spice vision can read spice netlist -> schematic

gateVision can read gate netlist (verliog netlist ?? ) -> schematic

 

[realtek]

I am also very curious about your perl script
if it works
Wow....
Can you share your perl script (send to me : mediatek@163.com)?
Thanks in advance!

 

[ram]

Sorry guys i cant do that..its company property. But here is some idea i will give how it works.
I am taking the library information from user. This information is library cell name & its equation in verilog form. If the cell can not be representated by equation then take a statement format this is taken using perl module (.pm file). Now read your netlist statement by statement.

For every cell instance in netlist replace it by the equation or statement taken from user. Here you have to change the pin name in equation or statement with the corrousponding instance pin name.

While doing this you have to take care of wild characters added by synopsys sush as /*cell* etc. Some function is necessary to replace such charcters by nonexisting name.

You may need to create new net (wire to connect 2-3 statements for one instance of tech. Lib cell).


By using this you can create a script. The script i have created is technilogy library specific. That will convert netlist in that technology to rtl.

The use of this convertion...can any guess?

Hope this will help you.

 

[xiongdh]

Sorry guys i cant do that..its company property. But here is some idea i will give how it works.
I am taking the library information from user. This information is library cell name & its equation in verilog form. If the cell can not be representated by equation then take a statement format this is taken using perl module (.pm file). Now read your netlist statement by statement.

For every cell instance in netlist replace it by the equation or statement taken from user. Here you have to change the pin name in equation or statement with the corrousponding instance pin name.

While doing this you have to take care of wild characters added by synopsys sush as /*cell* etc. Some function is necessary to replace such charcters by nonexisting name.

You may need to create new net (wire to connect 2-3 statements for one instance of tech. Lib cell).


By using this you can create a script. The script i have created is technilogy library specific. That will convert netlist in that technology to rtl.

The use of this convertion...can any guess?

Hope this will help you.

I see what you mean.
the convert rtl verilog is just only for simulation or synthesis,it is hard to understood.

 

[ram]

yes...xiongdh what you said is correct...

What i had observed is as follows ...
If i use this converted RTL for FPGA programming it will utilize less resources as compaired with original rtl. (I observed for some verilog codes)

I concluded that the optimization done by synopsys DC is better than synplify pro (my personal conclusion)

 

[okguy]

Here is a tool:
**broken link removed**

 

[yeewang]

what RAM did is to translate netlist in some format to netlist in verilog/vhdl format, that's what a lot of synthesis tool can do.

it won't help understanding the code, just for simulation or other tools those can only take HDL as input.

 

[Thinkie]

That TransEDA improve-TLL doesn't seem to exist anymore ...

Does any one have any links towards a netlist-to-RTL converter ?