Vernier interpolation

[manofwax]

vernier interpolation

Dear All,
I'm working on a project about time interval counter using vernier interpolation principle to get a higher resolution. If you are not family with vernier interpolation, it's totally fine, coz my question is quite general.

Here's my problem:
Input: Clk_ref with 100MHz
Input: Start_trigger
Output: Clk1 with 100MHz * (16/17) when the Start trigger signal goes high

I'm using virtex 4, I can easily get the output frequency with the DCM in FPGA. This is what I did. I fed the input clk_ref to the DCM and then I would get the output with the frequency that I want.

However, I don't want the output freq to be generated right away. I want it to happen AT THE MOMENT Start_trigger signal goes high.

Feeding the Clk1 and Start_trigger into an AND gate isn't an solution. Because the output of the AND gate will not go high at the moment(with some delay) Start_trigger go high. The output of the AND will just wait till Clk1 goes high.


This is what i want:
Clk_ref:xxxxxxxxxx|____|-----|____|-----|____|-----|____|-----|____|
Start_trigger:xxxxxx__________________|------------------------------------
Clk1:xxxxxxxxxxxxxx__________________|-------|_____|------|_____|------

Summary:
* freq of Clk1 = freq of Clk_ref * (16/17) <--- I can do this with DCM
* Clk1 will be triggered by Start_trigger;

Thanks in advance. Any suggestion and idea will be appreciated!!! Thanks.

 

[Iouri]

does DSM has PLL enable input?

 

[manofwax]

No, it only has a reset...

 

[manofwax]

Is it doable??? please help. Millions thanks

 

[echo47]

Vernier interpolation is a cool technique. I have a nice old HP 5370B sitting right here.

I suggest asking Xilinx (open a WebCase), but I think their answer will be "not possible".

You may need a different approach, such as passing your input signal through a high-speed delay line constructed from a carry chain, and then sample all the taps simultaneously. Requires careful placement constraints. I did some experiments in a Spartan-3, and achieved time measurement resolution of about 120ps. I could measure sub-nanosecond pulses. I think I used 42 taps sampled at 200 MHz. Must adjust the number of taps depending on the speed of the FPGA.

 

[manofwax]

Echo, i dont understand what u meant by "sample all the taps simultaneously", i dont quite understand rest of the stuff u mention either. Could you provide me more detail??

How can you achieve time measurement resolution of 120ps. Please feed me with more detail... Thanks...

 

[echo47]

I feed my input signal through a 42-bit carry chain. In a Spartan-3, it takes about 120ps for the input signal to propagate through each CLB (two MUXCY_L primitives), so this structure is basically a 5ns delay line with 42 taps. Next, I apply a 200 MHz clock to the FPGA. Inside each CLB, I connect the carry signal to a D-flop clocked at 200 MHz. The result - every 5ns the 42 D-flops take a snapshot of the input signal propagating along the delay line. The 42-bit output represents the input signal sampled at 120ps intervals, or 8.4 gigasamples per second.

If your FPGA's carry chain is faster or slower than 120ps, or if your clock is different from 200 MHz, then you need to adjust the number of taps accordingly. You will probably want to construct a mechanism that performs this adjustment automatically.

CLB placement is critical - the carry chain must fit into one column to achieve reasonably uniform 120ps delays.

Of course, you also need logic that analyzes the 42-bit output to find whatever you are looking for in the input signal.

This is stretching the limits of what can be done with an inexpensive FPGA. It's not a beginner FPGA project!

 

[banjo]

Is it possible to have some setup pulses on the start trigger? If so, you could use the phase adjustment tap of the DCM to shift the output to be aligned with the edge of the start trigger. Then you could use a simple AND gate, since start trigger and the clock output are aligned.
After training the phase of the DCM, your clock circuit should work as expected for the next application of the start trigger.
If you want to issue a start trigger at any time and with any possible phase relationship with respect to the clock, then I do not see an easy way to get the FPGA to do this. They are not designed to do such constant phase shifting clocks.
In my humble opinion, you either have some very tricky logic and hand routed FPGA work ahead of you or you must limit your spec to a simpler set of criteria for this version.

 

[manofwax]

Echo, as u can tell, i'm a newbie... =D thanks for the help. So you are not using implimenting the vernier technique?? Thanks. I'm going to digest ur suggestion now.

Banjo, Thanks for the help. Yup, the start trigger can go high any time.

Thank you very much for the ones who help!!! Can you tell me where I can gain some small and simple but realistic project to work on? Thanks!!!

 

[echo47]

I considered using the vernier interpolator technique in my project, but I couldn't think of any way to precisely start a good-stability oscillator inside the FPGA. I could have built an external oscillator, but my goal was to do everything, somehow, inside the FPGA.

For other project ideas, try exploring Xilinx application notes. You are bound to find something interesting.
**broken link removed**

I vaguely recall seeing the carry-chain delay line technique in one of those app notes.