how can resolve Delay problem with hdl code of interpolation FIR filter?

[noura7]

Hi all,

I have an interpolation FIR filter that i have simulatated with matlab simulink environement, there is delay when data is upsampled but this delay is becoming much when i describe this filter with vhdl code. How can i eleminate the delay difference between simulink and ModelSim?

Thanks a lot

Noura

 

[mwmmboy]

Did you added some pipeline stages?

 

[noura7]

no, it is a simple cascaded FIR structure

 

[TrickyDicky]

you need the pipeline stages or it wont work on an FPGA,.

 

[FvM]

You should give a brief idea of filter sampling rate and length.

Normally, there won't be more than a few clock cycles delay in addition to the filter length itself, except for extreme cases that run near the FPGA speed limits.

 

[noura7]

the filter length and sampling rate were about respectively 325 and 8 MHz.