// VerilogA for DLL_ideal, VCDL, veriloga
`include "constants.vams"
`include "disciplines.vams"
`timescale 1s/1ps
module VCDL (in, delay_control, out);
input in, delay_control;
output [0:7] out;
electrical in, delay_control;
electrical [0:7] int_node;
electrical [0:7] out;
VCDC VCDC0(in, int_node[0], delay_control);
VCDC VCDC1(int_node[0], int_node[1], delay_control);
VCDC VCDC2(int_node[1], int_node[2], delay_control);
VCDC VCDC3(int_node[2], int_node[3], delay_control);
VCDC VCDC4(int_node[3], int_node[4], delay_control);
VCDC VCDC5(int_node[4], int_node[5], delay_control);
VCDC VCDC6(int_node[5], int_node[6], delay_control);
VCDC VCDC7(int_node[6], int_node[7], delay_control);
analog begin
V(out[0]) <+ V(int_node[0]);
V(out[1]) <+ V(int_node[1]);
V(out[2]) <+ V(int_node[2]);
V(out[3]) <+ V(int_node[3]);
V(out[4]) <+ V(int_node[4]);
V(out[5]) <+ V(int_node[5]);
V(out[6]) <+ V(int_node[6]);
V(out[7]) <+ V(int_node[7]);
end
endmodule
`include "<the right directory>/VCDC/veriloga/veriloga.va"