VerilogA Transition Operator

[sumozgdyrqicsyhcnn]

Desired Behaviour:

Code:

module clk_gen(in, out)
input in;
output out;
electrical in, out;

parameter td = 100n;

real rise_abstime;

analog begin
    
    @(cross(V(in) - 900m, +1)) begin
        rise_abstime = $abstime;
    end
    
    @(timer(rise_abstime+td)) begin
        V(out) <+ transition(0, 1.8, 1n)
    end

end

I keep getting an error saying that the transition operator cannot be used nested in a conditional. How else am I supposed to cause a transition at particular point in time???

 

[jjx]

I think you want to do something like this instead:

module clk_gen(clk_in, clk_out);

input clk_in;
output clk_out;
electrical clk_in, clk_out;
parameter real td = 100n;
real clk_val = 0;
parameter vsup = 1.8;

analog begin
            @ ( cross(V(clk_in) - vsup/2.0, +1) ) begin
            clk_val = vsup;
        end
            @ ( cross(V(clk_in) - vsup/2.0, -1) ) begin
            clk_val = 0;
        end
    

    V(clk_out) <+  transition(clk_val, td, 1n, 1n);

end

endmodule