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VerilogA current limit for a voltage source

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Newbie level 4
Nov 15, 2015
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Hi all,

I made a model for a voltage-controlled voltage source (vcvs) that has both the output resistance and maximum current parameter as well.
However, I don't know why the current limit description seems not to work and causes the voltage source not to be functional as expected (i.e., the output of the voltage source is just 0V regardless of the input level). When I commented out the current limit block then I have a functional vcvs. The last time I added a current limit function to a block, it has the same description for the current limit, I wonder if there is something worth noticing if it is a vcvs that I am missing here. The code can be seen as below:

module cl_vcvs (vout_p, vout_n, vin_p, vin_n);

input vin_p, vin_n;
output vout_p, vout_n;
electrical vout_p, vout_n, vin_p, vin_n;

parameter real gain = 1;
parameter real Rout = 1m;
parameter real Ilim = 100m;

real iout;

analog begin
V(vout_p, vout_n) <+ gain*V(vin_p, vin_n);
iout = V(vout_p, vout_n)/Rout;

if (iout > Ilim) begin
iout = Ilim;
else if (iout < -Ilim) begin
iout = -Ilim;
I(vout_p, vout_n) <+ iout;


Thanks and best regards

My veriloga chops are not grande enough, to say whether
the case mismatches I see in the code have anything to do
with the problem. But cleaning that is where I'd start, just
to cross one "could be" off the list.

Iout == iout, or not?
Ilim == ilim, or not?
according to veriloga parsing

Then, I'm not sure about how the "if" statements for current
limit behave or are triggered.

If you don't need (and maybe you don't want) "sharp corners"
in your transfer function (which tend to make numerical
challenges for the simulator) you could consider a tanh()
type implementation - that will get you continuous derivatives
all the way out, you can get a resistance-ish region and two
current limit asymptotes but the transition "blends" in a smooth

But maybe you want a "brick wall" transfer characteristic
for some specific reason.

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