wandola
Junior Member level 3
Im doing monte carlo simulation of a clocked comparator. I want to save some signal data into a text file. So I wrote a small veriloga file to save the output. there is no problem.
But when I started running monte carlo, there were many many runs. So everytime when a new run starts, my saved data are overwritten.
I studied the veriloga mannual. I didn't find anything on file append. unlike C++, there is no "write","read","append"options in verilog. fstrobe,fwrite don't support appending data to an existing file.
does anybody know how to solve this issue?
I just want to append all monte carlo simulation data to a single file.
Thanks and regards.
But when I started running monte carlo, there were many many runs. So everytime when a new run starts, my saved data are overwritten.
I studied the veriloga mannual. I didn't find anything on file append. unlike C++, there is no "write","read","append"options in verilog. fstrobe,fwrite don't support appending data to an existing file.
does anybody know how to solve this issue?
I just want to append all monte carlo simulation data to a single file.
Thanks and regards.