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Verilog-XL simulation error

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lahaha

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When I tried to simulate a invertor with Verilog-XL, I got an two errors
(1)
Module or primitive (nmos3) not defined "ihnl/cds0/netlist", 19:nmos3 MN0(.D(Out),.G(In),.S(cds_globals.gnd-));
(2)
is similar to (1), but it is pmos3

I am using gpdk for this simulation. Is it the setting problem?
Please help!
 

yaxazaa

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have you include the primitive file?
 

lahaha

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How to include it?
Please help!
 

joe2moon

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Verilog-XL is a gate(cell) level simulator, not for transistor-level simulation.

If you want to simulate your invertor in SPICE, then you can
-1) change nmos3 to "nmos", and pmos3 to "pmos"
(nmos and pmos is Verilog pre-defined model.)

-2) Define your nmos3 and pmos3 modeling, ex: primitive

primitive your_mux (Y, A, B, S);
output Y;
input A, B, S;
table

// A B S : Y
//
1 ? 0 : 1 ;
0 ? 0 : 0 ;
? 1 1 : 1 ;
? 0 1 : 0 ;
0 0 x : 0 ;
1 1 x : 1 ;
endtable
endprimitive // your_mux
 

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