lahaha
Junior Member level 1
When I tried to simulate a invertor with Verilog-XL, I got an two errors
(1)
Module or primitive (nmos3) not defined "ihnl/cds0/netlist", 19:nmos3 MN0(.D(Out),.G(In),.S(cds_globals.gnd-));
(2)
is similar to (1), but it is pmos3
I am using gpdk for this simulation. Is it the setting problem?
Please help!
(1)
Module or primitive (nmos3) not defined "ihnl/cds0/netlist", 19:nmos3 MN0(.D(Out),.G(In),.S(cds_globals.gnd-));
(2)
is similar to (1), but it is pmos3
I am using gpdk for this simulation. Is it the setting problem?
Please help!