problem 1 you can't create asynchronous counters if you want something that will actually work on hardware. Verilog isn't like C programming it's a hardware description language and the bellow code does not describe a counter.
Code:
always @(start) begin
if (clk_divider == 4'b1000) begin // divided by 8
sck = ~sck;
end
if (clk_divider >= 4'b1000) begin
clk_divider [3:0] = 4'b0;
end
else begin
#1 clk_divider = clk_divider + 4'b1;
end
end
Your counter also doesn't do a divide by 8 it's a divide by 9.... 0,1,2,3,4,5,6,7,8 (there are 9 values before it repeats)
The #1 has no place in synthesizable code in my opinion. Besides that you don't have the timescale defined for this anywhere in the posted code. From the waveform it looks like it's defaulted to 1ns probably 1ns/1ps. So your clock is 500 MHz which is highly unlikely for SPI.
SCK doesn't toggle because both the initial value is X and stays X as there is no statements initializing it to a value at the start of simulation (not necessarily synthesizable) or a reset on the flip-flop generating it.
The typical way to "do" SPI is to use a much faster clock. You then sample the SPI bus (slave) and generate the SPI signals (master) using that faster clock domain. The only time you don't do this is if you have a design that does not have any clocks available when starting up, e.g. a design that programs the board VCOs that are used by the FPGA/CPLD. In such a case you have to use the SPI clock to run the slave interface.
I'm sure there are other problems, but I only glanced at your code.
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Edit...
Don't use positional port assignments it's a really bad practice and can render code un-maintainable or at minimum make it really easy to add a port and end up with a design that is no longer connected correctly. Instead use the named port association syntax.
e.g.
Code:
spi_master SPI_block(
.tx_data (tx_data),
.rx_data (rx_data),
.mosi (mosi),
.miso (miso),
.cs (cs),
.sck (sck),
.start (start),
.clk (clk)
);
If you add a new port it doesn't matter where you add the line assigning the new connection to the module.