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Verilog up-down counter. (help needed)

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EUverNE

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up down counter.v

Hi all,
I'm new in learning digital design for FPGA using Verilog HDL and encounter some difficulties trying to experiment designing a simple up_down counter. While compiling the design, Quartus v.9 web edition reports too many warnings regarding "combinatinal loops..." and "latches inferred for reg [out]...", and the simulator stops, reporting "zero-time oscillation on node..."

The code is:

module up_down_counter (up, down, reset, out);
input up, down, reset;
output out;
wire up, down, reset;
reg [3:0] out ;

always @ (negedge up, negedge down, negedge reset) begin
if (!reset)
out <= 0;
else if (!up)
out <= out + 1'b1;
else if (!down)
out <= out - 1'b1;
else
out <= out;
end

endmodule


I can't see where is the problem, and why i got those warning & errors. The textbooks doesn't seem to help enough, so any help greatly appreciated.

Thanks in advance
 

devas

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down counter

Hi,

You get all these messages because you do not use a real clock signal and your always sensitivity list should not be edge related when using comma seperated signals. The tools can nothing with this sensitivity list.

Add a real clock signal to the module and change the always sensitivity list into @(posedge clk or negedge reset)

Devas
 

EUverNE

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up/down counter

"...Add a real clock signal to the module and change the always sensitivity list into @(posedge clk or negedge reset)."

Hi Devas,

Thanks for your reply. I will correct the comma with "or" keyword but i have already tried adding a real clock, and i ended up with a design that counts "up" or "down" the clock pulses while the corresponding push button is been pressed.
I don't want to do that.

What i was thinking to do is to alter the value of a counter by one unit by pressing and releasing a button. In this case "up" to increase the counter value or "down" to decrease it. You may think of it like a volume up-down control.

I have successfully coded separate modules with increase or decrease only capability and they worked fine, but not a mix of both in one module.

e.g.

---Code for Up Counter---

module upcounter (up, out, reset);
input wire up, reset;
output reg [3:0] out;

always @ (negedge up or negedge reset)
if (~reset)
out <= 4'b0000;
else
out <= out +1'b1;

endmodule

Any ideas? I'm really stucked....
 

dcreddy1980

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counter verilog

module up_down_counter (up, down, reset, out);
input up, down, reset;
output out;
wire up, down, reset;
reg [3:0] out ;

wire up_down;
assign up_down = !up || !down;
always @ (posedge up_down or negedge reset) begin
if (!reset)
out <= 0;
else if (!up)
out <= out + 1'b1;
else if (!down)
out <= out - 1'b1;
else
out <= out;
end

endmodule

Check the above code, it might be the one which u r looking for. Some of the tools will complain about three edges in the sensitivity list.

I have created a signal called up_down which is high when up=0 or down =0. so this signals only will be active when u want to increment or decrement.

let me know if this is not what u want.

Regards,
dcreddy
 

EUverNE

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sample code for up-down counter application

IT WORKS!!!!
You hit the nail on the head!

I had tried variants of the basic code to no avail. I don't even remember how many days have been passed reading & coding again and again.
I feel relieved now!

Thank you very much dcreddy1980. :D :D


P.S.
Just for your information. The compiler reported the following warning but i will check it later on to see what it means.

Warning (10227): Verilog HDL Port Declaration warning at up_down_counter.v(47): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
 

EUverNE

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verilog how to check if a signal just changed

Oh' boy, here comes the pain again. :cry:

Just downloaded the code into the fpga board and nothing worked as it should. It worked fine in the simulator but not even close in real world. Both push-buttons (PB) decreased the counter by 2 units.
Performing timing analysis simulation it showed the truth. (see attachment)

The signals from top to bottom are :
UP
DOWN
OUT
RESET

Why this happened? It compiled perfectly without critical warnings . The warning message i mentioned earlier gone after correcting the declaration of "out" port.

Anyone?
 

dcreddy1980

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how to delay counter 1 clk in verilog

looking at the waveform, if you observe closely :

The OUT signal is changing 0-> 14 -> 12 -> 10 -> 8 -> 6 -> 4 -> 2 -> 0

14 -> 1110
12 -> 1100
10 -> 1010
8 -> 1000
6 -> 0110
4 -> 0100
2 -> 0010

I see the LSB is always zero???

Can u double check, whether OUT[0] is connected properly or some thing happened during synthesis for this bit. This should be a good starting point. I hope you got what i meant?

Can you drag the up_down signal in to the waveform, and check if you can see that signal behaviour?


Regards,
dcreddy
 

EUverNE

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verilog model+6 counter

Hi dcreddy,

Looking at the generated schematic diagram it seems that OUT[0] is properly connected to where it should be and is identical as the other OUT bits paths.

I notice that in the waveform results window, (see attachment) between OUT signal changes (e.g. 12->10) there is a dark area that makes the simulator's pointer to halt for a few fractions of time before advanced to the next state. Is this an indication of oscillation or something? Can this results in a malfunction?

Below is the waveform results. From top to bottom we see :

UP
DOWN
[3:0] OUT
RESET
UP_DOWN

During synthesis there are no reports for critical warnings neither errors. But time analyzer reports a message listed below:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected gated clock "up_down" as buffer

Is it critical?
 

dcreddy1980

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vhdl code for updown counter

I see that, we have to delay up_down signal

The up_down signal is a clock and at the same time, it looks at the changes in up and down signals, which can lead to setup and hold violation. Once the up_down signal is created, add couple of buffers so that u can capture stable up/down signals.

Make sure that you don't change the up/down signals very fastly i.e. less than the buffer delays which u will be adding. try this approach, it should work
 

j_andr

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verilog time counter

a nice example which you probably will never see in practice
but reveals some routing and timing features of fpga;
to on the 'bright side' of timing [not to be dependent
on placing and routing delays] you should write the code
this way:


Code:
module up_down_cnt (up, down, reset, out);
input        up, down, reset;
output [3:0] out;


wire up, down, reset;
reg [3:0] out ;

reg count_up, count_down;

always @(negedge up or negedge down)
  if (!down) count_up <= 1'b0;
  else       count_up <= 1'b1;

always @(negedge up or negedge down)
  if (!up)   count_down <= 1'b0;
  else       count_down <= 1'b1;


wire count_pulse = up & down;

always @ (posedge count_pulse or negedge reset) 
  begin
    if      (!reset)  out <= 4'h0;

    else if (count_up)     out <= out + 1'b1;
    else if (count_down)   out <= out - 1'b1;
    else                   out <= out;
end

endmodule

the idea is:
falling edge of up [down] sets a register count_up [count_down];
low level of up [down] signal clears count_down [count_up]
register;
in other words the counting direction is set;

rising edge of up or down signal creates a rising edge
of count_pulse - which is used to increment/decrement
the counter, depending of what count_up or count_down level
is active;
---
have fun
 

EUverNE

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design up-counter to down-counter

Hi dcreddy,

I see your point. We have one signal with dual role at the same time and that confuses the synthesis tool and we need to time separate the two functions. However in my textbooks i remember stating that is a bad programing technique to use buffers for creating delays because the resulting code is vendor dependent and hence not portable (and error prone). It is also a bad programing technique to use the "#0" delay code (don't remember why).


Hi j_andr,

Thanks for your reply. Although synthesis reported a few warnings regarding "skew" issues of "count_pulse", "up" and "down" signals, your code is working as expected both in simulator and hardware! :D
In a previous attempt of mine i have had successfully design a variation of the current design using one push-button and a slide switch (to set the count direction). I wanted to get rid of the slide switch and replace it with a second push button for days!!. You know what was next...


Although i have bought three textbooks (the latest was Morris Mano's Digital Design) i would like to hear some suggestions for new ones more practical and less bla bla that mention DO and DON'T regarding FPGA design techniques.


Thank you all for your time and inputs. You helped me go one step further in learning FPGA digital design. :D

Regards
 

dcreddy1980

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verilog counter

I didn't want you to put buffers manually, i wanted you to constrain the design properly during place and route and generate the clock i.e up_down signal in this case properly so that you don't see this weird behavior.

If you have proper constraining for this up_down signal, There will no problem in u r gate level simulation
 

EUverNE

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up down counter

At the time being I'm afraid that i don't know what is "constrain the design properly" and how to do it. :?

Do you mean that i have to adjust some options of the synthesis tool to auto insert a slight delay in the path of a preselected signal? (up_down in our case)
Currently I'm able to only use the basic functions of Quartus. :|
(Its manual spread across 2500 pages!!!)
 

chenbintom

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up_down_cnt

you design is a timing logic. it need a clock that you need to count.
 

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