Verilog time keyword.

[suhassmiley]

time event_start;

begin
event_start = $time;
end

why do we have to declare time event_start? we can simply declare event_start = $time?

 

[permute]

what is begin attached to?

 

[suhassmiley]

I just posted in general ok consider this

time save_sim_time;
initial
save_sim_time = $time;