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Verilog time keyword.

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suhassmiley

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time event_start;

begin
event_start = $time;
end

why do we have to declare time event_start? we can simply declare event_start = $time?
 

permute

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what is begin attached to?
 

suhassmiley

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I just posted in general ok consider this

time save_sim_time;
initial
save_sim_time = $time;
 

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