Verilog testbench, having instant/simultaneous access to block RAM?

[nervecell_23]

Hi,

When write a verilog testbench for a block RAM, is there any way to have instant access to the contents in a block RAM rather than giving address and waiting for a clock cycle? Namely something similar to having access to an register array. In addition, is it possible to read multiple contents from a block RAM by using unsynthesisable verilog?

Thanks!

 

[TrickyDicky]

If you did that, it wouldnt be a blockram any more, it would just be an array.

But why would you do that? this behaviour isnt supported for synthesis, so it wouldnt even be beneficial in a model.

 

[nervecell_23]

My DUT is an ALU that take inputs from a BRAM. I want to create a testbench that mimics its behaviour and validates the output.
I thought the testbench would be greatly simplified if there was any way to have instant/simultaneous access to the BRAM.
You are saying there's no way to do it yes?

 

[TrickyDicky]

That sounds like you're just trying to create a model. Then you can do whatever you like. Its not a BRAM, it only has to provide data to the DUT. You dont need a BRAM to do this, you can do whatever you want.
This is assuming you're not actually using a BRAM created by core-gen. If you're using this, you're stuck with the limitations of a BRAM.

 

[nervecell_23]

Right, I just want to create a model that mimics the behaviour of the actural ALU. But I want the model to take inputs from the real BRAM (created by core-gen rather than a reg-array) since the contents in the BRAM are the results of some other modules.
OK, I guess I have to do it just like how it works in real situation. Thanks.