Verilog testbench for CRC32

[Mavnus04]

Hi all,

I have used the website: http://outputlogic.com/?page_id=321 to generate a crc32 code for a 4-bit data wide. I am now in the process of making a test bench for the generated code. For some reason though, I am getting 0xFFFFFFFF as my result. Please help.

Thanks.

//generated code

module crc32(
  input [3:0] data,
  input enable,
  input reset,
  input clk,
  output [31:0] crc_out);

  reg [31:0] crc32_q,crc32_c;

  assign crc_out = crc32_q;

  always @(*) begin
    crc32_c[0] = crc32_q[28] ^ data[0];
    crc32_c[1] = crc32_q[28] ^ crc32_q[29] ^ data[0] ^ data[1];
    crc32_c[2] = crc32_q[28] ^ crc32_q[29] ^ crc32_q[30] ^ data[0] ^ data[1] ^ data[2];
    crc32_c[3] = crc32_q[29] ^ crc32_q[30] ^ crc32_q[31] ^ data[1] ^ data[2] ^ data[3];
    crc32_c[4] = crc32_q[0] ^ crc32_q[28] ^ crc32_q[30] ^ crc32_q[31] ^ data[0] ^ data[2] ^ data[3];
    crc32_c[5] = crc32_q[1] ^ crc32_q[28] ^ crc32_q[29] ^ crc32_q[31] ^ data[0] ^ data[1] ^ data[3];
    crc32_c[6] = crc32_q[2] ^ crc32_q[29] ^ crc32_q[30] ^ data[1] ^ data[2];
    crc32_c[7] = crc32_q[3] ^ crc32_q[28] ^ crc32_q[30] ^ crc32_q[31] ^ data[0] ^ data[2] ^ data[3];
    crc32_c[8] = crc32_q[4] ^ crc32_q[28] ^ crc32_q[29] ^ crc32_q[31] ^ data[0] ^ data[1] ^ data[3];
    crc32_c[9] = crc32_q[5] ^ crc32_q[29] ^ crc32_q[30] ^ data[1] ^ data[2];
    crc32_c[10] = crc32_q[6] ^ crc32_q[28] ^ crc32_q[30] ^ crc32_q[31] ^ data[0] ^ data[2] ^ data[3];
    crc32_c[11] = crc32_q[7] ^ crc32_q[28] ^ crc32_q[29] ^ crc32_q[31] ^ data[0] ^ data[1] ^ data[3];
    crc32_c[12] = crc32_q[8] ^ crc32_q[28] ^ crc32_q[29] ^ crc32_q[30] ^ data[0] ^ data[1] ^ data[2];
    crc32_c[13] = crc32_q[9] ^ crc32_q[29] ^ crc32_q[30] ^ crc32_q[31] ^ data[1] ^ data[2] ^ data[3];
    crc32_c[14] = crc32_q[10] ^ crc32_q[30] ^ crc32_q[31] ^ data[2] ^ data[3];
    crc32_c[15] = crc32_q[11] ^ crc32_q[31] ^ data[3];
    crc32_c[16] = crc32_q[12] ^ crc32_q[28] ^ data[0];
    crc32_c[17] = crc32_q[13] ^ crc32_q[29] ^ data[1];
    crc32_c[18] = crc32_q[14] ^ crc32_q[30] ^ data[2];
    crc32_c[19] = crc32_q[15] ^ crc32_q[31] ^ data[3];
    crc32_c[20] = crc32_q[16];
    crc32_c[21] = crc32_q[17];
    crc32_c[22] = crc32_q[18] ^ crc32_q[28] ^ data[0];
    crc32_c[23] = crc32_q[19] ^ crc32_q[28] ^ crc32_q[29] ^ data[0] ^ data[1];
    crc32_c[24] = crc32_q[20] ^ crc32_q[29] ^ crc32_q[30] ^ data[1] ^ data[2];
    crc32_c[25] = crc32_q[21] ^ crc32_q[30] ^ crc32_q[31] ^ data[2] ^ data[3];
    crc32_c[26] = crc32_q[22] ^ crc32_q[28] ^ crc32_q[31] ^ data[0] ^ data[3];
    crc32_c[27] = crc32_q[23] ^ crc32_q[29] ^ data[1];
    crc32_c[28] = crc32_q[24] ^ crc32_q[30] ^ data[2];
    crc32_c[29] = crc32_q[25] ^ crc32_q[31] ^ data[3];
    crc32_c[30] = crc32_q[26];
    crc32_c[31] = crc32_q[27];

  end // always

  always @(negedge clk, posedge reset) begin
    if(reset) begin
      crc32_q <= {32{1'b1}};
    end
    else begin
      crc32_q <= enable ? crc32_c : crc32_q;
    end
  end // always
endmodule // crc

//testbench

// Code your testbench here
//CRC32 test bench

module crc32_tb();

  reg clk, reset, enable;				//inputs to the CUT
  reg [3:0] data;
  wire [31:0] out;				//output of the CUT

  crc32 crc ( //the CUT
    .data(data),
    .enable(enable),
    .reset(reset),
    .clk(clk),
    .crc_out(out)
  ); 

initial begin

  $dumpfile("crc32.vcd");	//name of dump file to create
  $dumpvars(0, crc32_tb);	//record all signals of module crc32_tb and sub-modules

  //initial values
  clk = 0;
  reset = 0;
  enable = 0;
  data = 4'b0000;
  
  #1 reset = 1;
  #1 reset = 0;
  
  //start testing
  #1 enable = 1;
	 data = 4'b1011;
  

$finish;		//end the simulation
end

initial
  $monitor("At time %2t, enable = %d, reset = %d, in = %d, out = %d", 
           $time, enable, reset, data, out);

endmodule //crc32_tb

 

[ads-ee]

you need a forever loop in a separate initial block to generate a clock, otherwise the only crc32_q value that you will generate is the reset value.

Regards

 

[Mavnus04]

You mean like this:

always #1 clk = ~clk;

???

I added that, but still I only get the reset signal.

 

[ads-ee]

Did you even try googling "Verilog forever loop"? The first link returned was: https://www.asic-world.com/verilog/vbehave3.html

Which has the following code:

---

Code Verilog - [expand]
1
2
3
4
5
6
initial begin
  #1  clk = 0; 
  forever begin
  #5  clk = ~clk; 
  end
end

---

You should also add a `timescale directive in your testbench as the #<some_number> is using the simulator default. If it's the typical `timescale 1ns/1ps then you'll be generating a 500MHz clock when using #1. The example generates a 100 MHz clock (10 ns period).

Regards

 

[Mavnus04]

Thanks ads-ee.
So now that I have results from my crc code, how do I compare the expected with actual data?
My answer is 16'hABCD but I got 16'hAACD returned.
Thanks again.

 

[ads-ee]

This is a learning experience, you need to debug the code and determine if it is actually doing every step of the calculation correctly.