Verilog Synthesis Error

[Abdulquadir]

Hi Friends,

I have written a code for 8 bit RCA.
The file includes half adder, full adder and 8 bit RCA. I have compiled the code using VCS and it was successful. Further I have synthesis the script using synthesis script and genererated netlist.

From the generated netlist I am trying to compile the code again for which I am getting an error which states "Invalid Instantiation" I am not able to rectify this error Il b very helpful if some one will be able to guide me.

 

[rajavel.rv]

post your error message for our verification; and which software ur are using to compile the generated netlist its same VCS or other tool;

Regards
rajavel.rv