Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

C , VERILOG, VHDL.

C , VERILOG, VHDL.

Share this group

Quick Overview

Category
Uncategorized
Language
Total members
287
Total events
0
Total discussions
32
Total views
57K
Total albums
0

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

VErilog problem!with equation

Status
Not open for further replies.

akshay_sphere

Newbie level 1
Newbie level 1
Joined
Jan 23, 2015
Messages
0
Helped
0
Reputation
0
Reaction score
0
Trophy points
0
Activity points
0
suppose i want to display the output of the equation

A=Z/D

where Z=.002
and D=.125
here A is the output

how can i do this if i need an accurate result,ie i want to know will verilog be able to handle such a real value? if yes will it be synthezisable?
 

Status
Not open for further replies.
Top