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Need help on VHDL code for a 4 bit counter. with Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0

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jojo12

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-- Counter1bit
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter1bit is
port(
D, clk, clr : in bit; -- input
Q: out bit ); -- output
end counter1bit;
architecture behavior of counter1bit is
begin
process (clk,clr)
begin
if clr <= '0' then
Q <= '0';
elsif rising_edge (clk) then
Q<=D;
end if;
end process;
end behavior;
-- counter 4 bit
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
D: in bit_vector (3 downto 0); -- input
clr, clk : in bit; -- input
Q: out bit_vector (3 downto 0)); -- output
end counter;
architecture structure of counter is
component counter1bit
port(
D, clk , clr : in bit; -- input
Q: out bit ); -- output
end component;
begin --Instantiate 4 copies of the Flipflop
C0: counter1bit port map (D(0), Clr, Clk, Q(0));
C1: counter1bit port map (D(1), Clr, Clk, Q(1));
C2: counter1bit port map (D(2), Clr, Clk, Q(2));
C3: counter1bit port map (D(3), Clr, Clk, Q(3));
end structure;
architecture behavioral of counter is
begin
process is
begin
if D<9 then
Q <= Q+1;
elsif D>9 then
Q <= Q-1;
else
Q <= Q;
end if;
end process;
end behavioral;

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
D: in bit_vector (3 downto 0); -- input
clr, clk : in bit; -- input
Q: out bit_vector (3 downto 0)); -- output
end counter;
architecture structure of counter is
component counter1bit
port(
D, clk , clr : in bit; -- input
Q: out bit ); -- output
end component;
begin --Instantiate 4 copies of the Flipflop
C0: counter1bit port map (D(0), Clr, Clk, Q(0));
C1: counter1bit port map (D(1), Clr, Clk, Q(1));
C2: counter1bit port map (D(2), Clr, Clk, Q(2));
C3: counter1bit port map (D(3), Clr, Clk, Q(3));
end structure;
architecture behavioral of counter is
begin
process is
begin
if D<9 then
Q <= Q+1;
elsif D>9 then
Q <= Q-1;
else
Q <= Q;
end if;
end process;
end behavioral;

Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0 possible definitions
 

Without line numbers this is pretty difficult. But your statement “if clr <= '0' then” makes no sense; get rid of “<“.
 

Yes sorry, the error is at the line where it says "if D<9 then"
 

Without line numbers this is pretty difficult. But your statement “if clr <= '0' then” makes no sense; get rid of “<“.
Yes sorry, the error is at the line where it says "if D<9 then"
 

“process is begin” is not valid, either.
In my class, in slides that is how we write if statements in Quartus. It won't work without it.
 

Library std_logic_unsigned doesn't define operations for bit_vector. Use std_logic_vector instead of bit_vector to make the arithmetic operations work. Other errors will probably pop up then.

Most serious issue besides smaller syntax and library compatibilty problems: You can't make a counter without clock. The "behavioral" counter at the bottom of your code will never work in real FPGA hardware.
--- Updated ---

“process is begin” is not valid, either.
the "is" keyword is optional. but process needs a sensitivity list or a wait statement.
--- Updated ---

This works in hardware
Code:
process (clk) is
begin
    if rising_edge(clk) then
        if D<9 then
            Q <= Q+1;
        elsif D>9 then
            Q <= Q-1;
        else
            Q <= Q;
        end if;
    end if;
end process;
 
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