C , VERILOG, VHDL.

[karenmuller]

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY mult4 IS
PORT (
a, b : IN std_logic_vector(3 DOWNTO 0);
cout : OUT std_logic_vector(7 DOWNTO 0)
);
END mult4;

ARCHITECTURE behave OF mult4 IS
SIGNAL result : std_logic_vector(7 DOWNTO 0);
BEGIN
arith_process : PROCESS (a, b)
VARIABLE p : INTEGER RANGE 0 TO 255;

BEGIN
p := TO_INTEGER ('0' & a) * TO_INTEGER('0' & b);
result <= TO_STDLOGICVECTOR(p, 8);
END PROCESS arith_process;
cout <= result;
END behave;

I'm having a problem with TO_INTEGER, I tried to fix it but none worked, I'm new to VHDL and I'm not finding the solution.

Error (10405): VHDL error at mult4.vhd(19): can't determine type of object at or near identifier "TO_INTEGER" -- found 0 possible types

 

[barry]

to_integer takes UNSIGNED as an argument, not SLV. Simply cast your SLV to UNSIGNED.