Verilog syntax question

[alzomor]

verilog bus syntax ],

Hi

What is the meaning of this character "\" in verilog ?
and when it's used?
Whats the differenc between
.signal(\bus[0] )
and
.signal(bus[0] )

Salam
Hossam Alzomor
w ww.i-g.org

 

[uditkumar1983]

Hi,
\ Character is used at the beginning of escaped identifier ,
So For ".signal(bus[0] ) " value of bus[0] is passed ..
but in case of ".signal(\bus[0] ) " : Value of the variable defined using escaped identifier (\bus[0])is passed ..Which is different from simple from first case.......

Regards

 

[alzomor]

I don't understand what do you mean,

is the escape identifire some thing like "_" in c just a normal character like other characters?

Salam
Hossam Alzomor
ww.i-g.org

Added after 8 minutes:

Thanks

Now I understand what do you mean

.signal(bus[0] ) ==> means signal no 0 of the bus

.signal(\bus[0] ) ==> means the signal called \Bus[0]
Is that true?

Salam
Hossam Alzomor
ww.i-g.org