[SOLVED] verilog syntax question

[jmountney]

Can someone please help with the behavior of the following verilog code? I am not familiar with the " : " operation folowing an " always begin " statement. Is this some form of a conditional? Thank you.

 always 
   begin : x
      @(s); 
      begin

      
         ........   SOME CODE  .....



       end
end

 

[jrwebsterco]

It's an *optional* identifier (i.e. a label or name).
You only need it if you wish to reference it from a disable statement or to hierarchically reference local variables declared inside that sequential-block hierarchy.
(some simulators might also use it for more verbose log/debug messages if it exists)

I'd suggest grabbing a download of the unified SystemVerilog IEEE 1800-2012 SystemVerilog spec while it's still free:
It is now merged to cover both Verilog and SystemVerilog - you can see the description for block names in section 5.3.4.

 

[mrflibble]

As pointed out, it's a label. It's useful for example with a generate statement to give your instantiated modules more meaningful names.