Hello All,
Looking how a latch can be generated in Verilog/SV, normally the following case is cited:
- use of always@(*) where not all "reg" are updated (normally in cases where you have an "if" condition without a "else" condition when making combinational logic)
However, I have the feeling that the same condition can be achieved when using assign and ternary operator (?
, for example:
(note: code generated by head, might be inaccurate)
Code Verilog - [expand] |
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| reg [7:0] a;
always@(*)
begin
if (res) a = 8'h00;
else if (cond1) a = op1;
else if (cond2) a = op2;
end |
generates a latch, because there are conditions where "a" is not updated. This is equivalent of:
Code Verilog - [expand] |
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| wire [7:0] a;
assign a = res ? 8'h00 :
cond1 ? op1 :
cond2 ? op2 : a; |
But it seems the first one is always cited when generating latches and second one is never cited. Also, the tooling I use at the moment (Vivado 2018.3) does not detect latches in the second case.
I am missing something, or this is a case not covered normally, in a way even some (few? most? all?) tools cannot detect?