I receive an error when I attempt to assert or deassert the outputs directly in the state machine. I am missing something, and I know it is simple. Specifically, it is complaining the outputs are 'not of the register type'.
Code:
// Procedures.
always @(posedge CLOCK)
begin : SEQUENTIAL // Sequential logic block.
CURRENT_STATE <= NEXT_STATE;
end
always @(CURRENT_STATE)
begin : COMBINATORIAL // Combinatorial logic block.
case (CURRENT_STATE)
INITIAL:
begin
RESULT_LOAD <= 1'b0; // Errors result here.
TIMER_RESET <= 1'b1; // Errors result here.
T0 <= 24'd0;
T1 <= 24'd1;
ACCRUE_REG <= 24'd0;
end
endcase
end
Note for simplicity that the rest of the code is not shown.
What I posted is valid Verilog 2001 coding. That is except for the comma after RESULT_LOAD which I left as I assume there were more inputs/outputs following that output.
You'll actually see a lot of texts showing the older coding style...
Code Verilog - [expand]
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module xyz (a,b,c)output a;output b;input c;
personally I don't like using the non-C like port syntax.
Well, you would be violating a good practice by NOT registering it. That being the good practice of registering your module outputs.
Another vote for the verilog 2001 style module declaration. Saves typing and makes your code more readable than the old school lets-repeat-things-34987345-times style.