Jun 9, 2009 #1 V vlsi_freak Full Member level 2 Joined Sep 3, 2007 Messages 127 Helped 14 Reputation 28 Reaction score 8 Trophy points 1,298 Activity points 2,041 Verilog State Assignment Hi All, In VHDL, we can write same set of logic for multiple states as shown below, when STATE_A | STATE_B => ---- ----- How we write an equivalent logic in Verilog. Please help me. regards, freak
Verilog State Assignment Hi All, In VHDL, we can write same set of logic for multiple states as shown below, when STATE_A | STATE_B => ---- ----- How we write an equivalent logic in Verilog. Please help me. regards, freak
Jun 10, 2009 #2 T teja321 Member level 1 Joined Oct 16, 2006 Messages 37 Helped 6 Reputation 12 Reaction score 1 Trophy points 1,288 Activity points 1,483 Re: Verilog State Assignment STATE_A,STATE_B :
Jan 22, 2010 #3 S sudhirkv Advanced Member level 4 Joined Dec 13, 2005 Messages 106 Helped 8 Reputation 16 Reaction score 1 Trophy points 1,298 Location Chennai, India Activity points 1,992 u can use always @ (STATEA or STATEB)
Jan 22, 2010 #4 S Syswip Advanced Member level 4 Joined Nov 11, 2009 Messages 119 Helped 12 Reputation 24 Reaction score 4 Trophy points 1,298 Activity points 1,859 Hi vlsi_freak, In Verilog for FSM you should use case() ... endcase and you should assign your next state inside case block. If you explain what do you want to to you'll get better help. Best Regards,
Hi vlsi_freak, In Verilog for FSM you should use case() ... endcase and you should assign your next state inside case block. If you explain what do you want to to you'll get better help. Best Regards,