Verilog simulation with Virtuoso and cadence tools

[cipher_crypto]

simulating verilog virtuoso

Hi,
I was designing a FFT processor with verilog. When I was using virtuoso tool I faced problem. My code worked well in Xilinx.
FFT1 << top module
butterfly3 is instance of another module radix1. Now I am getting error message like this "Error: Netlister unable to descend any of the views defined in the view list "verilog schematic extracted" for instance butterfly 3 in cell FFT1. Either one of these views to library FFT1_lib cell: radix1 modify the view list to ....an existing view"
I already listed this radix1 in my system....
Please let me know how to solve this problem...

cipher

 

[linuxluo]

virtuoso verilog simulation

hi,
I think you should use ncsim to verification but not virtusso which is a layout and schmetic tools.

 

[cipher_crypto]

Thank you linux.Well basically I need to do it with Virtuoso cadence. I am note sure what making the tool give that error msg. I am sure the mistake might be very simple.

 

[ecijun]

You need check .simrc file.

 

[cipher_crypto]

hi Ecijun
Thank you. What is .simrc file? Which directory I will find it?