cipher_crypto
Junior Member level 3
simulating verilog virtuoso
Hi,
I was designing a FFT processor with verilog. When I was using virtuoso tool I faced problem. My code worked well in Xilinx.
FFT1 << top module
butterfly3 is instance of another module radix1. Now I am getting error message like this "Error: Netlister unable to descend any of the views defined in the view list "verilog schematic extracted" for instance butterfly 3 in cell FFT1. Either one of these views to library FFT1_lib cell: radix1 modify the view list to ....an existing view"
I already listed this radix1 in my system....
Please let me know how to solve this problem...
cipher
Hi,
I was designing a FFT processor with verilog. When I was using virtuoso tool I faced problem. My code worked well in Xilinx.
FFT1 << top module
butterfly3 is instance of another module radix1. Now I am getting error message like this "Error: Netlister unable to descend any of the views defined in the view list "verilog schematic extracted" for instance butterfly 3 in cell FFT1. Either one of these views to library FFT1_lib cell: radix1 modify the view list to ....an existing view"
I already listed this radix1 in my system....
Please let me know how to solve this problem...
cipher