Verilog: Simple Pulse Generator/ Clock Divider

[lendo1]

Hello everyone, I am working on a simple program that creates an output Pulse every (input) N clock cycles. The logic is very simple, but I am new to Verilog and am having problems assigning my output (Pulse.) Any ideas? Thanks!

module pulse_atN(Clk, Reset, Pulse, N);	

	parameter WIDTH = 10;

	input		Clk, Reset;
	input [WIDTH-1:0] N;	
	reg [WIDTH-1:0] Nlast;	

	
	reg [WIDTH-1:0] Count;	

	output Pulse;
	
	assign Pulse = (Count == N-1) && (N != 0); 

		
	always @ (posedge Clk, posedge Reset)
	begin : PULSE_GENERATOR
		if(Reset)
			Count <= 0;
		else
			begin
		    	// nonblocking so check occurs with old Nlast
    			Nlast <= N;
   
		    	if(Nlast != N)
		      		Count <= 0;
        		else if(Count == N-1)
          			begin
						Count <= 0;
						Pulse = 1;

          			end
			  	else
			  		begin
						Count <= Count + 1;
						Pulse = 0;

					end
		  end
	end
	
endmodule

 

[lendo1]

"Illegal Reference to net: Pulse" in my else if and else blocks. How do I correctly assign it??

 

[ads_ee]

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
module pulse_at_N  #(
  parameter pWIDTH = 10
) (
  input                     CLK,
  input                     RESET,
  input       [pWIDTH-1:0]  N,
  output reg  [pWIDTH-1:0]  PULSE
);
 
 
  reg [pWIDTH-1:0]  count;
 
  always @ (posedge CLK, posedge RESET) begin : PULSE_GENERATOR
 
    // counter:
    // this could be made a down counter starting at N-1 so the compare becomes a reduction operation.
    // i.e. ~|count, which detects a 0 value.
    if ( RESET ) begin
      count <= 0;       // could use {pWIDTH{1'b0}} to avoid truncating messages
    end else begin
      count <= (count < N) ? count + 1 : 0;
    end
 
    // pulse generator
    PULSE <= (count == N-1) ? 1 : 0;
 
  end
 
endmodule

---

This should work. Take a look at the differences in this and your code. I made the counter just a N rollover counter and a separate statement to produce the pulse based on the count value.
You should play around with the down count as it's more efficient to do a reduction operation than a full compare.

 

[lendo1]

Ahh yes that works but the larger file which I have no control of declares Pulse as a wire. For some reason, I can't figure out how to update the value of Pulse without getting all these errors! (either "LHS in procedural continuous statement may not be a net: Pulse" or "Illegal Reference to net: Pulse"

 

[ads_ee]

Ahh yes that works but the larger file which I have no control of declares Pulse as a wire. For some reason, I can't figure out how to update the value of Pulse without getting all these errors! (either "LHS in procedural continuous statement may not be a net: Pulse" or "Illegal Reference to net: Pulse"

Then change pulse in the code to pulse_reg and then add assign pulse = pulse_reg; to the code.

- - - Updated - - -

Hmmm, if this pulse_atn module is instantiated somewhere and you're seeing issues outside this module you've got something else going on.

my assign pulse = pulse_reg; won't fix something in the level above. Having the Pulse module port defined as reg won't affect how it gets hooked up in the level above.