Newbie level 3
Hello everyone, I am working on a simple program that creates an output Pulse every (input) N clock cycles. The logic is very simple, but I am new to Verilog and am having problems assigning my output (Pulse.) Any ideas? Thanks!
module pulse_atN(Clk, Reset, Pulse, N); parameter WIDTH = 10; input Clk, Reset; input [WIDTH-1:0] N; reg [WIDTH-1:0] Nlast; reg [WIDTH-1:0] Count; output Pulse; assign Pulse = (Count == N-1) && (N != 0); always @ (posedge Clk, posedge Reset) begin : PULSE_GENERATOR if(Reset) Count <= 0; else begin // nonblocking so check occurs with old Nlast Nlast <= N; if(Nlast != N) Count <= 0; else if(Count == N-1) begin Count <= 0; Pulse = 1; end else begin Count <= Count + 1; Pulse = 0; end end end endmodule