Jun 20, 2019 #1 B beginner_EDA Full Member level 4 Joined Aug 14, 2013 Messages 191 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 3,854 Hi, I came across following generated code from vivado: Code Verilog - [expand]1 2 3 4 5 6 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) some_ip some_ip_inst( .a(a), .b(b) ); I know to set parameter inside module we use this way: some_ip Code Verilog - [expand]1 2 3 4 5 6 7 8 #( .EXAMPLE_SIMULATION (1), .SIM_SPEEDUP ("FALSE") ) some_ip_inst( .a(a), .b(b) ); or use defparam to overreide : defparam hierarchical_path = paratemter value; but I didn't understand which kind of syntax is this? Code Verilog - [expand]1 2 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) can anybody explain it? Last edited by a moderator: Jun 20, 2019
Hi, I came across following generated code from vivado: Code Verilog - [expand]1 2 3 4 5 6 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) some_ip some_ip_inst( .a(a), .b(b) ); I know to set parameter inside module we use this way: some_ip Code Verilog - [expand]1 2 3 4 5 6 7 8 #( .EXAMPLE_SIMULATION (1), .SIM_SPEEDUP ("FALSE") ) some_ip_inst( .a(a), .b(b) ); or use defparam to overreide : defparam hierarchical_path = paratemter value; but I didn't understand which kind of syntax is this? Code Verilog - [expand]1 2 (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) can anybody explain it?
Jun 20, 2019 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 The (* some_attribute = some_value *) are for synthesis attributes. Though in this case the attributes don't look like synthesis attributes, they must be custom attributes. They certainly don't show up as attributes in the synthesis guide.
The (* some_attribute = some_value *) are for synthesis attributes. Though in this case the attributes don't look like synthesis attributes, they must be custom attributes. They certainly don't show up as attributes in the synthesis guide.