verilog rtl handling interrupt trig n interruprt clear simultaneously needed ?

[wls]

Hello . I am writing an timer counter with apb interface (slave) . At each overflow count or input capture signal , a pulse trigger is generated . The interrupt enable register , interrrupt register and clear interrupt register reside at apb slave side ? If the clear register is set (1) , the interrupt is clear and clear is auto clear.

How do i write a verilog rtl to handle simultaneous interrupt signal and clear signal , if both trigger same time . Can anyone give example of rtl code of handling clear interrupt and interrupt simultaneously.

Long time , i didnt write verilog , most forgot.

Appreciate the help .....

REgards.

 

[ravurig]

In rtl, poll for Interrupt status it.
If set clear interrupt.

If you are using "arm" easy testbench, modify C-code to add an ISR routine.

 

[wls]

Hello . I am writing verilog testbench to test it ? Do we need to consider the previous interrupt and next interrupt ? Let say clear and int trigger happen simultaneously . The clear should clear the previous interrupt and same time int trigger is set by the present interrupt ? Do u have sample verilog code ? I attached the pdf of int n clear logic possibilities . int trig is set when int is detected , so possibilities is it is set by previous int . Thus clear should cear the previous one and int trig can be set by new int . Once clear , clear the int trig , it will auto clear .

Hope can give example ?

Thx.