Verilog reg declaration @ and gate output

[whenyoureachme]

Hi All,

I am very new to VERILOG programming as my first program i have wrote an andgate program in the gate level abstraction with inputs x, y and output z. Here is my first program

module andgate (z, x, y);
input x, y;
output z;
wire x, y;
reg z; ---------- // I end up with an Syntax Error if i use this statement.

and (z,x,y);

endmodule


Please help me in understanding the reason why we are unable to declare reg z; at this instance

Thanks in Advance:razz:

 

[RBB]

Should be: wire z;

 

[Jack// ani]

Gate level abstraction is similar to continuous assignment. That means output is valid as long as input is applied, there is no data storage.

When you place register at the output you're trying to store output which is not valid, however, you can use procedural block to achieve this.

Hope this helps

 

[whenyoureachme]

Gate level abstraction is similar to continuous assignment. That means output is valid as long as input is applied, there is no data storage.

When you place register at the output you're trying to store output which is not valid, however, you can use procedural block to achieve this.

Hope this helps

Thank U Mr. Jack.

 

[permute]

verilog basically calls anything that is assigned in an always or initial block a "reg", even if it doesn't infer a register. things assigned outside are generally declared as wire. systemverilog defines a "logic" type that can be used in most cases.

 

[yadog]

permute presents exactly the keypoint

in verilog,reg not equals to a physical register!

And in some case,you must use reg.

Have try,have fun!